1 /** 2 * \file 3 * 4 * \brief Instance description for SERCOM5 5 * 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20_SERCOM5_INSTANCE_ 48 #define _SAMD20_SERCOM5_INSTANCE_ 49 50 /* ========== Register definition for SERCOM5 peripheral ========== */ 51 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 52 #define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ 53 #define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ 54 #define REG_SERCOM5_I2CM_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Control */ 55 #define REG_SERCOM5_I2CM_BAUD (0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate */ 56 #define REG_SERCOM5_I2CM_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ 57 #define REG_SERCOM5_I2CM_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ 58 #define REG_SERCOM5_I2CM_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ 59 #define REG_SERCOM5_I2CM_STATUS (0x42001C10U) /**< \brief (SERCOM5) I2CM Status */ 60 #define REG_SERCOM5_I2CM_ADDR (0x42001C14U) /**< \brief (SERCOM5) I2CM Address */ 61 #define REG_SERCOM5_I2CM_DATA (0x42001C18U) /**< \brief (SERCOM5) I2CM Data */ 62 #define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ 63 #define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ 64 #define REG_SERCOM5_I2CS_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ 65 #define REG_SERCOM5_I2CS_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ 66 #define REG_SERCOM5_I2CS_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ 67 #define REG_SERCOM5_I2CS_STATUS (0x42001C10U) /**< \brief (SERCOM5) I2CS Status */ 68 #define REG_SERCOM5_I2CS_ADDR (0x42001C14U) /**< \brief (SERCOM5) I2CS Address */ 69 #define REG_SERCOM5_I2CS_DATA (0x42001C18U) /**< \brief (SERCOM5) I2CS Data */ 70 #define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ 71 #define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ 72 #define REG_SERCOM5_SPI_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) SPI Debug Control */ 73 #define REG_SERCOM5_SPI_BAUD (0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate */ 74 #define REG_SERCOM5_SPI_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ 75 #define REG_SERCOM5_SPI_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ 76 #define REG_SERCOM5_SPI_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ 77 #define REG_SERCOM5_SPI_STATUS (0x42001C10U) /**< \brief (SERCOM5) SPI Status */ 78 #define REG_SERCOM5_SPI_ADDR (0x42001C14U) /**< \brief (SERCOM5) SPI Address */ 79 #define REG_SERCOM5_SPI_DATA (0x42001C18U) /**< \brief (SERCOM5) SPI Data */ 80 #define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */ 81 #define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */ 82 #define REG_SERCOM5_USART_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) USART Debug Control */ 83 #define REG_SERCOM5_USART_BAUD (0x42001C0AU) /**< \brief (SERCOM5) USART Baud */ 84 #define REG_SERCOM5_USART_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ 85 #define REG_SERCOM5_USART_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set */ 86 #define REG_SERCOM5_USART_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ 87 #define REG_SERCOM5_USART_STATUS (0x42001C10U) /**< \brief (SERCOM5) USART Status */ 88 #define REG_SERCOM5_USART_DATA (0x42001C18U) /**< \brief (SERCOM5) USART Data */ 89 #else 90 #define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ 91 #define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ 92 #define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Control */ 93 #define REG_SERCOM5_I2CM_BAUD (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate */ 94 #define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ 95 #define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ 96 #define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ 97 #define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CM Status */ 98 #define REG_SERCOM5_I2CM_ADDR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Address */ 99 #define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Data */ 100 #define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ 101 #define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ 102 #define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ 103 #define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ 104 #define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ 105 #define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CS Status */ 106 #define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C14U) /**< \brief (SERCOM5) I2CS Address */ 107 #define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Data */ 108 #define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ 109 #define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ 110 #define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) SPI Debug Control */ 111 #define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate */ 112 #define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ 113 #define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ 114 #define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ 115 #define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) SPI Status */ 116 #define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C14U) /**< \brief (SERCOM5) SPI Address */ 117 #define REG_SERCOM5_SPI_DATA (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) SPI Data */ 118 #define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */ 119 #define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */ 120 #define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) USART Debug Control */ 121 #define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) USART Baud */ 122 #define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ 123 #define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set */ 124 #define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ 125 #define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) USART Status */ 126 #define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) USART Data */ 127 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 128 129 /* ========== Instance parameters for SERCOM5 peripheral ========== */ 130 #define SERCOM5_GCLK_ID_CORE 18 131 #define SERCOM5_GCLK_ID_SLOW 12 132 #define SERCOM5_INT_MSB 3 133 #define SERCOM5_PMSB 3 134 135 #endif /* _SAMD20_SERCOM5_INSTANCE_ */ 136