1 /** 2 * \file 3 * 4 * \brief Instance description for SYSCTRL 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20_SYSCTRL_INSTANCE_ 48 #define _SAMD20_SYSCTRL_INSTANCE_ 49 50 /* ========== Register definition for SYSCTRL peripheral ========== */ 51 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 52 #define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ 53 #define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ 54 #define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ 55 #define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ 56 #define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) XOSC Control */ 57 #define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control */ 58 #define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) OSC32K Control */ 59 #define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control */ 60 #define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) OSC8M Control A */ 61 #define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL Config */ 62 #define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value */ 63 #define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier */ 64 #define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization */ 65 #define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ 66 #define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) VREG Control */ 67 #define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) VREF Control A */ 68 #else 69 #define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ 70 #define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ 71 #define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ 72 #define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ 73 #define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) XOSC Control */ 74 #define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control */ 75 #define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) OSC32K Control */ 76 #define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control */ 77 #define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) OSC8M Control A */ 78 #define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL Config */ 79 #define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value */ 80 #define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier */ 81 #define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization */ 82 #define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ 83 #define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) VREG Control */ 84 #define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) VREF Control A */ 85 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 /* ========== Instance parameters for SYSCTRL peripheral ========== */ 88 #define SYSCTRL_BGAP_CALIB_MSB 11 89 #define SYSCTRL_BOD33_CALIB_MSB 5 90 #define SYSCTRL_DFLL48M_COARSE_MSB 4 91 #define SYSCTRL_DFLL48M_FINE_MSB 7 92 #define SYSCTRL_GCLK_ID_DFLL48 0 93 #define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 94 #define SYSCTRL_POR33_ENTEST_MSB 1 95 #define SYSCTRL_ULPVREF_DIVLEV_MSB 3 96 #define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 97 #define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 98 #define SYSCTRL_VREF_CONTROL_MSB 48 99 #define SYSCTRL_VREF_STATUS_MSB 7 100 #define SYSCTRL_VREG_LEVEL_MSB 2 101 #define SYSCTRL_BOD12_VERSION 0x111 102 #define SYSCTRL_BOD33_VERSION 0x111 103 #define SYSCTRL_DFLL48M_VERSION 0x211 104 #define SYSCTRL_GCLK_VERSION 0x210 105 #define SYSCTRL_OSCULP32K_VERSION 0x111 106 #define SYSCTRL_OSC8M_VERSION 0x120 107 #define SYSCTRL_OSC32K_VERSION 0x1101 108 #define SYSCTRL_VREF_VERSION 0x200 109 #define SYSCTRL_VREG_VERSION 0x201 110 #define SYSCTRL_XOSC_VERSION 0x1101 111 #define SYSCTRL_XOSC32K_VERSION 0x1101 112 113 #endif /* _SAMD20_SYSCTRL_INSTANCE_ */ 114