1 /** 2 * \file 3 * 4 * \brief Header file for SAMD20E15 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20E15_ 48 #define _SAMD20E15_ 49 50 /** 51 * \ingroup SAMD20_definitions 52 * \addtogroup SAMD20E15_definitions SAMD20E15 definitions 53 * This file defines all structures and symbols for SAMD20E15: 54 * - registers and bitfields 55 * - peripheral base address 56 * - peripheral ID 57 * - PIO definitions 58 */ 59 /*@{*/ 60 61 #ifdef __cplusplus 62 extern "C" { 63 #endif 64 65 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 66 #include <stdint.h> 67 #ifndef __cplusplus 68 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 69 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 70 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 71 #else 72 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 73 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 74 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 75 #endif 76 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 77 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 78 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 79 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 80 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 81 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 82 #define CAST(type, value) ((type *)(value)) 83 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ 84 #else 85 #define CAST(type, value) (value) 86 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ 87 #endif 88 89 /* ************************************************************************** */ 90 /** CMSIS DEFINITIONS FOR SAMD20E15 */ 91 /* ************************************************************************** */ 92 /** \defgroup SAMD20E15_cmsis CMSIS Definitions */ 93 /*@{*/ 94 95 /** Interrupt Number Definition */ 96 typedef enum IRQn 97 { 98 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ 99 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 100 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ 101 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ 102 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ 103 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ 104 /****** SAMD20E15-specific Interrupt Numbers ***********************/ 105 PM_IRQn = 0, /**< 0 SAMD20E15 Power Manager (PM) */ 106 SYSCTRL_IRQn = 1, /**< 1 SAMD20E15 System Control (SYSCTRL) */ 107 WDT_IRQn = 2, /**< 2 SAMD20E15 Watchdog Timer (WDT) */ 108 RTC_IRQn = 3, /**< 3 SAMD20E15 Real-Time Counter (RTC) */ 109 EIC_IRQn = 4, /**< 4 SAMD20E15 External Interrupt Controller (EIC) */ 110 NVMCTRL_IRQn = 5, /**< 5 SAMD20E15 Non-Volatile Memory Controller (NVMCTRL) */ 111 EVSYS_IRQn = 6, /**< 6 SAMD20E15 Event System Interface (EVSYS) */ 112 SERCOM0_IRQn = 7, /**< 7 SAMD20E15 Serial Communication Interface 0 (SERCOM0) */ 113 SERCOM1_IRQn = 8, /**< 8 SAMD20E15 Serial Communication Interface 1 (SERCOM1) */ 114 SERCOM2_IRQn = 9, /**< 9 SAMD20E15 Serial Communication Interface 2 (SERCOM2) */ 115 SERCOM3_IRQn = 10, /**< 10 SAMD20E15 Serial Communication Interface 3 (SERCOM3) */ 116 TC0_IRQn = 13, /**< 13 SAMD20E15 Basic Timer Counter 0 (TC0) */ 117 TC1_IRQn = 14, /**< 14 SAMD20E15 Basic Timer Counter 1 (TC1) */ 118 TC2_IRQn = 15, /**< 15 SAMD20E15 Basic Timer Counter 2 (TC2) */ 119 TC3_IRQn = 16, /**< 16 SAMD20E15 Basic Timer Counter 3 (TC3) */ 120 TC4_IRQn = 17, /**< 17 SAMD20E15 Basic Timer Counter 4 (TC4) */ 121 TC5_IRQn = 18, /**< 18 SAMD20E15 Basic Timer Counter 5 (TC5) */ 122 ADC_IRQn = 21, /**< 21 SAMD20E15 Analog Digital Converter (ADC) */ 123 AC_IRQn = 22, /**< 22 SAMD20E15 Analog Comparators (AC) */ 124 DAC_IRQn = 23, /**< 23 SAMD20E15 Digital Analog Converter (DAC) */ 125 PTC_IRQn = 24, /**< 24 SAMD20E15 Peripheral Touch Controller (PTC) */ 126 127 PERIPH_COUNT_IRQn = 25 /**< Number of peripheral IDs */ 128 } IRQn_Type; 129 130 typedef struct _DeviceVectors 131 { 132 /* Stack pointer */ 133 void* pvStack; 134 135 /* Cortex-M handlers */ 136 void* pfnReset_Handler; 137 void* pfnNMI_Handler; 138 void* pfnHardFault_Handler; 139 void* pfnReservedM12; 140 void* pfnReservedM11; 141 void* pfnReservedM10; 142 void* pfnReservedM9; 143 void* pfnReservedM8; 144 void* pfnReservedM7; 145 void* pfnReservedM6; 146 void* pfnSVC_Handler; 147 void* pfnReservedM4; 148 void* pfnReservedM3; 149 void* pfnPendSV_Handler; 150 void* pfnSysTick_Handler; 151 152 /* Peripheral handlers */ 153 void* pfnPM_Handler; /* 0 Power Manager */ 154 void* pfnSYSCTRL_Handler; /* 1 System Control */ 155 void* pfnWDT_Handler; /* 2 Watchdog Timer */ 156 void* pfnRTC_Handler; /* 3 Real-Time Counter */ 157 void* pfnEIC_Handler; /* 4 External Interrupt Controller */ 158 void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ 159 void* pfnEVSYS_Handler; /* 6 Event System Interface */ 160 void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */ 161 void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */ 162 void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */ 163 void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */ 164 void* pfnReserved11; 165 void* pfnReserved12; 166 void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */ 167 void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */ 168 void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */ 169 void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */ 170 void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */ 171 void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */ 172 void* pfnReserved19; 173 void* pfnReserved20; 174 void* pfnADC_Handler; /* 21 Analog Digital Converter */ 175 void* pfnAC_Handler; /* 22 Analog Comparators */ 176 void* pfnDAC_Handler; /* 23 Digital Analog Converter */ 177 void* pfnPTC_Handler; /* 24 Peripheral Touch Controller */ 178 } DeviceVectors; 179 180 /* Cortex-M0+ processor handlers */ 181 void Reset_Handler ( void ); 182 void NMI_Handler ( void ); 183 void HardFault_Handler ( void ); 184 void SVC_Handler ( void ); 185 void PendSV_Handler ( void ); 186 void SysTick_Handler ( void ); 187 188 /* Peripherals handlers */ 189 void PM_Handler ( void ); 190 void SYSCTRL_Handler ( void ); 191 void WDT_Handler ( void ); 192 void RTC_Handler ( void ); 193 void EIC_Handler ( void ); 194 void NVMCTRL_Handler ( void ); 195 void EVSYS_Handler ( void ); 196 void SERCOM0_Handler ( void ); 197 void SERCOM1_Handler ( void ); 198 void SERCOM2_Handler ( void ); 199 void SERCOM3_Handler ( void ); 200 void TC0_Handler ( void ); 201 void TC1_Handler ( void ); 202 void TC2_Handler ( void ); 203 void TC3_Handler ( void ); 204 void TC4_Handler ( void ); 205 void TC5_Handler ( void ); 206 void ADC_Handler ( void ); 207 void AC_Handler ( void ); 208 void DAC_Handler ( void ); 209 void PTC_Handler ( void ); 210 211 /* 212 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 213 */ 214 215 #define LITTLE_ENDIAN 1 216 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 217 #define __MPU_PRESENT 0 /*!< MPU present or not */ 218 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 219 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 220 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 221 222 /** 223 * \brief CMSIS includes 224 */ 225 226 #include <core_cm0plus.h> 227 #if !defined DONT_USE_CMSIS_INIT 228 #include "system_samd20.h" 229 #endif /* DONT_USE_CMSIS_INIT */ 230 231 /*@}*/ 232 233 /* ************************************************************************** */ 234 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E15 */ 235 /* ************************************************************************** */ 236 /** \defgroup SAMD20E15_api Peripheral Software API */ 237 /*@{*/ 238 239 #include "component/ac.h" 240 #include "component/adc.h" 241 #include "component/dac.h" 242 #include "component/dsu.h" 243 #include "component/eic.h" 244 #include "component/evsys.h" 245 #include "component/gclk.h" 246 #include "component/nvmctrl.h" 247 #include "component/pac.h" 248 #include "component/pm.h" 249 #include "component/port.h" 250 #include "component/rtc.h" 251 #include "component/sercom.h" 252 #include "component/sysctrl.h" 253 #include "component/tc.h" 254 #include "component/wdt.h" 255 /*@}*/ 256 257 /* ************************************************************************** */ 258 /** REGISTERS ACCESS DEFINITIONS FOR SAMD20E15 */ 259 /* ************************************************************************** */ 260 /** \defgroup SAMD20E15_reg Registers Access Definitions */ 261 /*@{*/ 262 263 #include "instance/ac.h" 264 #include "instance/adc.h" 265 #include "instance/dac.h" 266 #include "instance/dsu.h" 267 #include "instance/eic.h" 268 #include "instance/evsys.h" 269 #include "instance/gclk.h" 270 #include "instance/nvmctrl.h" 271 #include "instance/pac0.h" 272 #include "instance/pac1.h" 273 #include "instance/pac2.h" 274 #include "instance/pm.h" 275 #include "instance/port.h" 276 #include "instance/rtc.h" 277 #include "instance/sercom0.h" 278 #include "instance/sercom1.h" 279 #include "instance/sercom2.h" 280 #include "instance/sercom3.h" 281 #include "instance/sysctrl.h" 282 #include "instance/tc0.h" 283 #include "instance/tc1.h" 284 #include "instance/tc2.h" 285 #include "instance/tc3.h" 286 #include "instance/tc4.h" 287 #include "instance/tc5.h" 288 #include "instance/wdt.h" 289 /*@}*/ 290 291 /* ************************************************************************** */ 292 /** PERIPHERAL ID DEFINITIONS FOR SAMD20E15 */ 293 /* ************************************************************************** */ 294 /** \defgroup SAMD20E15_id Peripheral Ids Definitions */ 295 /*@{*/ 296 297 // Peripheral instances on HPB0 bridge 298 #define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ 299 #define ID_PM 1 /**< \brief Power Manager (PM) */ 300 #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ 301 #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ 302 #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ 303 #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ 304 #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ 305 306 // Peripheral instances on HPB1 bridge 307 #define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ 308 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 309 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 310 #define ID_PORT 35 /**< \brief Port Module (PORT) */ 311 312 // Peripheral instances on HPB2 bridge 313 #define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ 314 #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ 315 #define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 316 #define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 317 #define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 318 #define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 319 #define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ 320 #define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ 321 #define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ 322 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ 323 #define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ 324 #define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ 325 #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ 326 #define ID_AC 81 /**< \brief Analog Comparators (AC) */ 327 #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ 328 #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ 329 330 #define ID_PERIPH_COUNT 84 /**< \brief Number of peripheral IDs */ 331 /*@}*/ 332 333 /* ************************************************************************** */ 334 /** BASE ADDRESS DEFINITIONS FOR SAMD20E15 */ 335 /* ************************************************************************** */ 336 /** \defgroup SAMD20E15_base Peripheral Base Address Definitions */ 337 /*@{*/ 338 339 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 340 #define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ 341 #define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ 342 #define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ 343 #define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ 344 #define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ 345 #define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ 346 #define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ 347 #define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 348 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 349 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 350 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 351 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 352 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 353 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 354 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 355 #define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ 356 #define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ 357 #define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ 358 #define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ 359 #define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ 360 #define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 361 #define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ 362 #define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ 363 #define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ 364 #define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ 365 #define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ 366 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ 367 #define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ 368 #define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ 369 #define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ 370 #define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ 371 #define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ 372 #define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ 373 #define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ 374 #else 375 #define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ 376 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 377 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 378 379 #define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ 380 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 381 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 382 383 #define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ 384 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 385 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 386 387 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 388 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 389 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 390 391 #define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ 392 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 393 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 394 395 #define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ 396 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 397 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 398 399 #define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ 400 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 401 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 402 403 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 404 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 405 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 406 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 407 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 408 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 409 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 410 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 411 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 412 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 413 414 #define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ 415 #define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ 416 #define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ 417 #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ 418 #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ 419 420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 421 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 422 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 423 424 #define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ 425 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 426 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 427 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 428 429 #define PTC_GCLK_ID 27 430 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 431 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 432 433 #define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ 434 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 435 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 436 437 #define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ 438 #define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ 439 #define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ 440 #define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ 441 #define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ 442 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ 443 444 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ 445 #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ 446 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ 447 448 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ 449 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ 450 #define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ 451 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ 452 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ 453 #define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ 454 #define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ 455 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ 456 457 #define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ 458 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 459 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 460 461 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 462 /*@}*/ 463 464 /* ************************************************************************** */ 465 /** PORT DEFINITIONS FOR SAMD20E15 */ 466 /* ************************************************************************** */ 467 /** \defgroup SAMD20E15_port PORT Definitions */ 468 /*@{*/ 469 470 #include "pio/samd20e15.h" 471 /*@}*/ 472 473 /* ************************************************************************** */ 474 /** MEMORY MAPPING DEFINITIONS FOR SAMD20E15 */ 475 /* ************************************************************************** */ 476 477 #define FLASH_SIZE 0x8000UL /* 32 kB */ 478 #define FLASH_PAGE_SIZE 64 479 #define FLASH_NB_OF_PAGES 512 480 #define FLASH_USER_PAGE_SIZE 64 481 #define HRAMC0_SIZE 0x1000UL /* 4 kB */ 482 #define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ 483 #define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ 484 #define HRAMC0_ADDR (0x20000000UL) /**< HRAMC0 base address */ 485 486 #define DSU_DID_RESETVALUE 0x1000130DUL 487 #define PORT_GROUPS 1 488 489 /* ************************************************************************** */ 490 /** ELECTRICAL DEFINITIONS FOR SAMD20E15 */ 491 /* ************************************************************************** */ 492 493 494 #ifdef __cplusplus 495 } 496 #endif 497 498 /*@}*/ 499 500 #endif /* SAMD20E15_H */ 501