1 /** 2 * \file 3 * 4 * \brief Instance description for ADC 5 * 6 * Copyright (c) 2016 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef _SAMD21_ADC_INSTANCE_ 45 #define _SAMD21_ADC_INSTANCE_ 46 47 /* ========== Register definition for ADC peripheral ========== */ 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ 50 #define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ 51 #define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ 52 #define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ 53 #define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ 54 #define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ 55 #define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ 56 #define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ 57 #define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ 58 #define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ 59 #define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ 60 #define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ 61 #define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ 62 #define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ 63 #define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ 64 #define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ 65 #define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ 66 #define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ 67 #define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ 68 #define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ 69 #else 70 #define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ 71 #define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ 72 #define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ 73 #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ 74 #define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ 75 #define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ 76 #define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ 77 #define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ 78 #define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ 79 #define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ 80 #define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ 81 #define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ 82 #define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ 83 #define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ 84 #define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ 85 #define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ 86 #define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ 87 #define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ 88 #define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ 89 #define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ 90 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 /* ========== Instance parameters for ADC peripheral ========== */ 93 #define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger 94 #define ADC_EXTCHANNEL_MSB 19 // Number of external channels 95 #define ADC_GCLK_ID 30 // Index of Generic Clock 96 #define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield 97 #define ADC_RESULT_MSB 15 // Size of Result 98 99 #endif /* _SAMD21_ADC_INSTANCE_ */ 100