1 /** 2 * \file 3 * 4 * \brief Header file for SAMD21G15A 5 * 6 * Copyright (c) 2016 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef _SAMD21G15A_ 45 #define _SAMD21G15A_ 46 47 /** 48 * \ingroup SAMD21_definitions 49 * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions 50 * This file defines all structures and symbols for SAMD21G15A: 51 * - registers and bitfields 52 * - peripheral base address 53 * - peripheral ID 54 * - PIO definitions 55 */ 56 /*@{*/ 57 58 #ifdef __cplusplus 59 extern "C" { 60 #endif 61 62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 63 #include <stdint.h> 64 #ifndef __cplusplus 65 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 66 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 67 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 68 #else 69 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 70 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 71 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 72 #endif 73 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 74 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 75 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 76 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 77 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 78 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 79 #define CAST(type, value) ((type *)(value)) 80 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ 81 #else 82 #define CAST(type, value) (value) 83 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ 84 #endif 85 86 /* ************************************************************************** */ 87 /** CMSIS DEFINITIONS FOR SAMD21G15A */ 88 /* ************************************************************************** */ 89 /** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ 90 /*@{*/ 91 92 /** Interrupt Number Definition */ 93 typedef enum IRQn 94 { 95 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ 96 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 97 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ 98 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ 99 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ 100 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ 101 /****** SAMD21G15A-specific Interrupt Numbers ***********************/ 102 PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ 103 SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ 104 WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ 105 RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ 106 EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ 107 NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ 108 DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ 109 USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ 110 EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ 111 SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ 112 SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ 113 SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ 114 SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ 115 SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ 116 SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ 117 TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ 118 TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ 119 TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ 120 TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ 121 TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ 122 TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ 123 ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ 124 AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ 125 DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ 126 PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ 127 I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ 128 129 PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ 130 } IRQn_Type; 131 132 typedef struct _DeviceVectors 133 { 134 /* Stack pointer */ 135 void* pvStack; 136 137 /* Cortex-M handlers */ 138 void* pfnReset_Handler; 139 void* pfnNMI_Handler; 140 void* pfnHardFault_Handler; 141 void* pvReservedM12; 142 void* pvReservedM11; 143 void* pvReservedM10; 144 void* pvReservedM9; 145 void* pvReservedM8; 146 void* pvReservedM7; 147 void* pvReservedM6; 148 void* pfnSVC_Handler; 149 void* pvReservedM4; 150 void* pvReservedM3; 151 void* pfnPendSV_Handler; 152 void* pfnSysTick_Handler; 153 154 /* Peripheral handlers */ 155 void* pfnPM_Handler; /* 0 Power Manager */ 156 void* pfnSYSCTRL_Handler; /* 1 System Control */ 157 void* pfnWDT_Handler; /* 2 Watchdog Timer */ 158 void* pfnRTC_Handler; /* 3 Real-Time Counter */ 159 void* pfnEIC_Handler; /* 4 External Interrupt Controller */ 160 void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ 161 void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ 162 void* pfnUSB_Handler; /* 7 Universal Serial Bus */ 163 void* pfnEVSYS_Handler; /* 8 Event System Interface */ 164 void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ 165 void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ 166 void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ 167 void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ 168 void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ 169 void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ 170 void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ 171 void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ 172 void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ 173 void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ 174 void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ 175 void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ 176 void* pvReserved21; 177 void* pvReserved22; 178 void* pfnADC_Handler; /* 23 Analog Digital Converter */ 179 void* pfnAC_Handler; /* 24 Analog Comparators */ 180 void* pfnDAC_Handler; /* 25 Digital Analog Converter */ 181 void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ 182 void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ 183 void* pvReserved28; 184 } DeviceVectors; 185 186 /* Cortex-M0+ processor handlers */ 187 void Reset_Handler ( void ); 188 void NMI_Handler ( void ); 189 void HardFault_Handler ( void ); 190 void SVC_Handler ( void ); 191 void PendSV_Handler ( void ); 192 void SysTick_Handler ( void ); 193 194 /* Peripherals handlers */ 195 void PM_Handler ( void ); 196 void SYSCTRL_Handler ( void ); 197 void WDT_Handler ( void ); 198 void RTC_Handler ( void ); 199 void EIC_Handler ( void ); 200 void NVMCTRL_Handler ( void ); 201 void DMAC_Handler ( void ); 202 void USB_Handler ( void ); 203 void EVSYS_Handler ( void ); 204 void SERCOM0_Handler ( void ); 205 void SERCOM1_Handler ( void ); 206 void SERCOM2_Handler ( void ); 207 void SERCOM3_Handler ( void ); 208 void SERCOM4_Handler ( void ); 209 void SERCOM5_Handler ( void ); 210 void TCC0_Handler ( void ); 211 void TCC1_Handler ( void ); 212 void TCC2_Handler ( void ); 213 void TC3_Handler ( void ); 214 void TC4_Handler ( void ); 215 void TC5_Handler ( void ); 216 void ADC_Handler ( void ); 217 void AC_Handler ( void ); 218 void DAC_Handler ( void ); 219 void PTC_Handler ( void ); 220 void I2S_Handler ( void ); 221 222 /* 223 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 224 */ 225 226 #define LITTLE_ENDIAN 1 227 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 228 #define __MPU_PRESENT 0 /*!< MPU present or not */ 229 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 230 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 231 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 232 233 /** 234 * \brief CMSIS includes 235 */ 236 237 #include <core_cm0plus.h> 238 #if !defined DONT_USE_CMSIS_INIT 239 #include "system_samd21.h" 240 #endif /* DONT_USE_CMSIS_INIT */ 241 242 /*@}*/ 243 244 /* ************************************************************************** */ 245 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ 246 /* ************************************************************************** */ 247 /** \defgroup SAMD21G15A_api Peripheral Software API */ 248 /*@{*/ 249 250 #include "component/ac.h" 251 #include "component/adc.h" 252 #include "component/dac.h" 253 #include "component/dmac.h" 254 #include "component/dsu.h" 255 #include "component/eic.h" 256 #include "component/evsys.h" 257 #include "component/gclk.h" 258 #include "component/hmatrixb.h" 259 #include "component/i2s.h" 260 #include "component/mtb.h" 261 #include "component/nvmctrl.h" 262 #include "component/pac.h" 263 #include "component/pm.h" 264 #include "component/port.h" 265 #include "component/rtc.h" 266 #include "component/sercom.h" 267 #include "component/sysctrl.h" 268 #include "component/tc.h" 269 #include "component/tcc.h" 270 #include "component/usb.h" 271 #include "component/wdt.h" 272 /*@}*/ 273 274 /* ************************************************************************** */ 275 /** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ 276 /* ************************************************************************** */ 277 /** \defgroup SAMD21G15A_reg Registers Access Definitions */ 278 /*@{*/ 279 280 #include "instance/ac.h" 281 #include "instance/adc.h" 282 #include "instance/dac.h" 283 #include "instance/dmac.h" 284 #include "instance/dsu.h" 285 #include "instance/eic.h" 286 #include "instance/evsys.h" 287 #include "instance/gclk.h" 288 #include "instance/sbmatrix.h" 289 #include "instance/i2s.h" 290 #include "instance/mtb.h" 291 #include "instance/nvmctrl.h" 292 #include "instance/pac0.h" 293 #include "instance/pac1.h" 294 #include "instance/pac2.h" 295 #include "instance/pm.h" 296 #include "instance/port.h" 297 #include "instance/rtc.h" 298 #include "instance/sercom0.h" 299 #include "instance/sercom1.h" 300 #include "instance/sercom2.h" 301 #include "instance/sercom3.h" 302 #include "instance/sercom4.h" 303 #include "instance/sercom5.h" 304 #include "instance/sysctrl.h" 305 #include "instance/tc3.h" 306 #include "instance/tc4.h" 307 #include "instance/tc5.h" 308 #include "instance/tcc0.h" 309 #include "instance/tcc1.h" 310 #include "instance/tcc2.h" 311 #include "instance/usb.h" 312 #include "instance/wdt.h" 313 /*@}*/ 314 315 /* ************************************************************************** */ 316 /** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ 317 /* ************************************************************************** */ 318 /** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ 319 /*@{*/ 320 321 // Peripheral instances on HPB0 bridge 322 #define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ 323 #define ID_PM 1 /**< \brief Power Manager (PM) */ 324 #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ 325 #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ 326 #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ 327 #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ 328 #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ 329 330 // Peripheral instances on HPB1 bridge 331 #define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ 332 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 333 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 334 #define ID_PORT 35 /**< \brief Port Module (PORT) */ 335 #define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ 336 #define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ 337 #define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 338 #define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ 339 340 // Peripheral instances on HPB2 bridge 341 #define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ 342 #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ 343 #define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 344 #define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 345 #define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 346 #define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 347 #define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 348 #define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 349 #define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ 350 #define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ 351 #define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ 352 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ 353 #define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ 354 #define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ 355 #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ 356 #define ID_AC 81 /**< \brief Analog Comparators (AC) */ 357 #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ 358 #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ 359 #define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ 360 361 #define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ 362 /*@}*/ 363 364 /* ************************************************************************** */ 365 /** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ 366 /* ************************************************************************** */ 367 /** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ 368 /*@{*/ 369 370 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 371 #define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ 372 #define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ 373 #define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ 374 #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ 375 #define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ 376 #define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ 377 #define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ 378 #define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ 379 #define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ 380 #define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ 381 #define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ 382 #define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 383 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 384 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 385 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 386 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 387 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 388 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 389 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 390 #define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ 391 #define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ 392 #define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ 393 #define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ 394 #define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ 395 #define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 396 #define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ 397 #define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ 398 #define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ 399 #define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ 400 #define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ 401 #define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ 402 #define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ 403 #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ 404 #define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ 405 #define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ 406 #define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ 407 #define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ 408 #define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ 409 #define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ 410 #define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ 411 #define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ 412 #else 413 #define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ 414 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 415 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 416 417 #define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ 418 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 419 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 420 421 #define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ 422 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 423 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 424 425 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ 426 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 427 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 428 429 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 430 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 431 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 432 433 #define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ 434 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 435 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 436 437 #define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ 438 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 439 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 440 441 #define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ 442 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 443 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 444 445 #define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ 446 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 447 #define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ 448 449 #define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ 450 #define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ 451 #define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ 452 453 #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ 454 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 455 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 456 457 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 458 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 459 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 460 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 461 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 462 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 463 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 464 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 465 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 466 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 467 468 #define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ 469 #define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ 470 #define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ 471 #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ 472 #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ 473 474 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 475 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 476 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 477 478 #define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ 479 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 480 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 481 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 482 483 #define PTC_GCLK_ID 34 484 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 485 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 486 487 #define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ 488 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 489 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 490 491 #define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ 492 #define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ 493 #define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ 494 #define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ 495 #define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ 496 #define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ 497 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 498 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 499 500 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ 501 #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ 502 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ 503 504 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ 505 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ 506 #define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ 507 #define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ 508 #define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ 509 510 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ 511 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ 512 #define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ 513 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 514 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 515 516 #define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ 517 #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ 518 #define USB_INSTS { USB } /**< \brief (USB) Instances List */ 519 520 #define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ 521 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 522 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 523 524 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 525 /*@}*/ 526 527 /* ************************************************************************** */ 528 /** PORT DEFINITIONS FOR SAMD21G15A */ 529 /* ************************************************************************** */ 530 /** \defgroup SAMD21G15A_port PORT Definitions */ 531 /*@{*/ 532 533 #include "pio/samd21g15a.h" 534 /*@}*/ 535 536 /* ************************************************************************** */ 537 /** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ 538 /* ************************************************************************** */ 539 540 #define FLASH_SIZE 0x8000UL /* 32 kB */ 541 #define FLASH_PAGE_SIZE 64 542 #define FLASH_NB_OF_PAGES 512 543 #define FLASH_USER_PAGE_SIZE 64 544 #define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ 545 546 #define FLASH_ADDR (0x00000000u) /**< FLASH base address */ 547 #define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ 548 #define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ 549 #define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ 550 #define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ 551 #define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ 552 #define PPB_ADDR (0xE0000000u) /**< PPB base address */ 553 554 #define DSU_DID_RESETVALUE 0x10010008UL 555 #define EIC_EXTINT_NUM 16 556 #define PORT_GROUPS 2 557 558 /* ************************************************************************** */ 559 /** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ 560 /* ************************************************************************** */ 561 562 563 #ifdef __cplusplus 564 } 565 #endif 566 567 /*@}*/ 568 569 #endif /* SAMD21G15A_H */ 570