1 /**************************************************************************//**
2 * @file core_cm3.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 * @version V1.30
5 * @date 30. October 2009
6 *
7 * @note
8 * Copyright (C) 2009 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 /*******************************************************************************
24 * Microsemi SoC Products Group SVN revision number for the purpose of tracking
25 * changes done to original file supplied by ARM:
26 * SVN $Revision: 4048 $
27 * SVN $Date: 2011-12-06 16:05:56 +0000 (Tue, 06 Dec 2011) $
28 ******************************************************************************/
29
30 #ifndef __CM3_CORE_H__
31 #define __CM3_CORE_H__
32
33 /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
34 *
35 * List of Lint messages which will be suppressed and not shown:
36 * - Error 10: \n
37 * register uint32_t __regBasePri __asm("basepri"); \n
38 * Error 10: Expecting ';'
39 * .
40 * - Error 530: \n
41 * return(__regBasePri); \n
42 * Warning 530: Symbol '__regBasePri' (line 264) not initialized
43 * .
44 * - Error 550: \n
45 * __regBasePri = (basePri & 0x1ff); \n
46 * Warning 550: Symbol '__regBasePri' (line 271) not accessed
47 * .
48 * - Error 754: \n
49 * uint32_t RESERVED0[24]; \n
50 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
51 * .
52 * - Error 750: \n
53 * #define __CM3_CORE_H__ \n
54 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
55 * .
56 * - Error 528: \n
57 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
58 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
59 * .
60 * - Error 751: \n
61 * } InterruptType_Type; \n
62 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
63 * .
64 * Note: To re-enable a Message, insert a space before 'lint' *
65 *
66 */
67
68 /*lint -save */
69 /*lint -e10 */
70 /*lint -e530 */
71 /*lint -e550 */
72 /*lint -e754 */
73 /*lint -e750 */
74 /*lint -e528 */
75 /*lint -e751 */
76
77
78 /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
79 This file defines all structures and symbols for CMSIS core:
80 - CMSIS version number
81 - Cortex-M core registers and bitfields
82 - Cortex-M core peripheral base address
83 @{
84 */
85
86 #ifdef __cplusplus
87 extern "C" {
88 #endif
89
90 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
91 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
92 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
93
94 #define __CORTEX_M (0x03) /*!< Cortex core */
95
96 #include <stdint.h> /* Include standard types */
97
98 #if defined (__ICCARM__)
99 #include <intrinsics.h> /* IAR Intrinsics */
100 #endif
101
102
103 #ifndef __NVIC_PRIO_BITS
104 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
105 #endif
106
107
108
109
110 /**
111 * IO definitions
112 *
113 * define access restrictions to peripheral registers
114 */
115
116 #ifdef __cplusplus
117 #define __I volatile /*!< defines 'read only' permissions */
118 #else
119 #define __I volatile const /*!< defines 'read only' permissions */
120 #endif
121 #define __O volatile /*!< defines 'write only' permissions */
122 #define __IO volatile /*!< defines 'read / write' permissions */
123
124
125
126 /*******************************************************************************
127 * Register Abstraction
128 ******************************************************************************/
129 /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
130 @{
131 */
132
133
134 /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
135 memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
136 @{
137 */
138 typedef struct
139 {
140 __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
141 uint32_t RESERVED0[24];
142 __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
143 uint32_t RSERVED1[24];
144 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
145 uint32_t RESERVED2[24];
146 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
147 uint32_t RESERVED3[24];
148 __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
149 uint32_t RESERVED4[56];
150 __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
151 uint32_t RESERVED5[644];
152 __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
153 } NVIC_Type;
154 /*@}*/ /* end of group CMSIS_CM3_NVIC */
155
156
157 /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
158 memory mapped structure for System Control Block (SCB)
159 @{
160 */
161 typedef struct
162 {
163 __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
164 __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
165 __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
166 __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
167 __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
168 __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
169 __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
170 __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
171 __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
172 __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
173 __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
174 __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
175 __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
176 __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
177 __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
178 __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
179 __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
180 __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
181 __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
182 } SCB_Type;
183
184 /* SCB CPUID Register Definitions */
185 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
186 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
187
188 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
189 #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
190
191 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
192 #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
193
194 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
195 #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
196
197 /* SCB Interrupt Control State Register Definitions */
198 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
199 #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
200
201 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
202 #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
203
204 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
205 #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
206
207 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
208 #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
209
210 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
211 #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
212
213 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
214 #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
215
216 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
217 #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
218
219 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
220 #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
221
222 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
223 #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
224
225 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
226 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
227
228 /* SCB Interrupt Control State Register Definitions */
229 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
230 #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
231
232 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
233 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
234
235 /* SCB Application Interrupt and Reset Control Register Definitions */
236 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
237 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
238
239 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
240 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
241
242 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
243 #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
244
245 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
246 #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
247
248 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
249 #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
250
251 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
252 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
253
254 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
255 #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
256
257 /* SCB System Control Register Definitions */
258 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
259 #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
260
261 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
262 #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
263
264 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
265 #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
266
267 /* SCB Configuration Control Register Definitions */
268 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
269 #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
270
271 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
272 #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
273
274 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
275 #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
276
277 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
278 #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
279
280 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
281 #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
282
283 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
284 #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
285
286 /* SCB System Handler Control and State Register Definitions */
287 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
288 #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
289
290 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
291 #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
292
293 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
294 #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
295
296 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
297 #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
298
299 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
300 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
301
302 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
303 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
304
305 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
306 #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
307
308 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
309 #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
310
311 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
312 #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
313
314 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
315 #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
316
317 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
318 #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
319
320 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
321 #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
322
323 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
324 #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
325
326 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
327 #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
328
329 /* SCB Configurable Fault Status Registers Definitions */
330 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
331 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
332
333 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
334 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
335
336 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
337 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
338
339 /* SCB Hard Fault Status Registers Definitions */
340 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
341 #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
342
343 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
344 #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
345
346 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
347 #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
348
349 /* SCB Debug Fault Status Register Definitions */
350 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
351 #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
352
353 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
354 #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
355
356 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
357 #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
358
359 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
360 #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
361
362 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
363 #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
364 /*@}*/ /* end of group CMSIS_CM3_SCB */
365
366
367 /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
368 memory mapped structure for SysTick
369 @{
370 */
371 typedef struct
372 {
373 __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
374 __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
375 __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
376 __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
377 } SysTick_Type;
378
379 /* SysTick Control / Status Register Definitions */
380 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
381 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
382
383 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
384 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
385
386 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
387 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
388
389 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
390 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
391
392 /* SysTick Reload Register Definitions */
393 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
394 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
395
396 /* SysTick Current Register Definitions */
397 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
398 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
399
400 /* SysTick Calibration Register Definitions */
401 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
402 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
403
404 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
405 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
406
407 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
408 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
409 /*@}*/ /* end of group CMSIS_CM3_SysTick */
410
411
412 /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
413 memory mapped structure for Instrumentation Trace Macrocell (ITM)
414 @{
415 */
416 typedef struct
417 {
418 __O union
419 {
420 __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
421 __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
422 __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
423 } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
424 uint32_t RESERVED0[864];
425 __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
426 uint32_t RESERVED1[15];
427 __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
428 uint32_t RESERVED2[15];
429 __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
430 uint32_t RESERVED3[29];
431 __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
432 __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
433 __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
434 uint32_t RESERVED4[43];
435 __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
436 __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
437 uint32_t RESERVED5[6];
438 __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
439 __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
440 __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
441 __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
442 __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
443 __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
444 __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
445 __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
446 __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
447 __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
448 __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
449 __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
450 } ITM_Type;
451
452 /* ITM Trace Privilege Register Definitions */
453 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
454 #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
455
456 /* ITM Trace Control Register Definitions */
457 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
458 #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
459
460 #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
461 #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
462
463 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
464 #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
465
466 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
467 #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
468
469 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
470 #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
471
472 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
473 #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
474
475 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
476 #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
477
478 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
479 #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
480
481 /* ITM Integration Write Register Definitions */
482 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
483 #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
484
485 /* ITM Integration Read Register Definitions */
486 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
487 #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
488
489 /* ITM Integration Mode Control Register Definitions */
490 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
491 #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
492
493 /* ITM Lock Status Register Definitions */
494 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
495 #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
496
497 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
498 #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
499
500 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
501 #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
502 /*@}*/ /* end of group CMSIS_CM3_ITM */
503
504
505 /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
506 memory mapped structure for Interrupt Type
507 @{
508 */
509 typedef struct
510 {
511 uint32_t RESERVED0;
512 __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
513 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
514 __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
515 #else
516 uint32_t RESERVED1;
517 #endif
518 } InterruptType_Type;
519
520 /* Interrupt Controller Type Register Definitions */
521 #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
522 #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
523
524 /* Auxiliary Control Register Definitions */
525 #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
526 #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
527
528 #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
529 #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
530
531 #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
532 #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
533 /*@}*/ /* end of group CMSIS_CM3_InterruptType */
534
535
536 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
537 /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
538 memory mapped structure for Memory Protection Unit (MPU)
539 @{
540 */
541 typedef struct
542 {
543 __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
544 __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
545 __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
546 __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
547 __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
548 __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
549 __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
550 __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
551 __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
552 __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
553 __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
554 } MPU_Type;
555
556 /* MPU Type Register */
557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
558 #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
559
560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
561 #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
562
563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
564 #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
565
566 /* MPU Control Register */
567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
568 #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
569
570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
571 #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
572
573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
574 #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
575
576 /* MPU Region Number Register */
577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
578 #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
579
580 /* MPU Region Base Address Register */
581 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
582 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
583
584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
585 #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
586
587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
588 #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
589
590 /* MPU Region Attribute and Size Register */
591 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
592 #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
593
594 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
595 #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
596
597 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
598 #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
599
600 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
601 #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
602
603 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
604 #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
605
606 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
607 #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
608
609 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
610 #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
611
612 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
613 #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
614
615 #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
616 #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
617
618 /*@}*/ /* end of group CMSIS_CM3_MPU */
619 #endif
620
621
622 /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
623 memory mapped structure for Core Debug Register
624 @{
625 */
626 typedef struct
627 {
628 __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
629 __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
630 __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
631 __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
632 } CoreDebug_Type;
633
634 /* Debug Halting Control and Status Register */
635 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
636 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
637
638 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
639 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
640
641 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
642 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
643
644 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
645 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
646
647 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
648 #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
649
650 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
651 #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
652
653 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
654 #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
655
656 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
657 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
658
659 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
660 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
661
662 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
663 #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
664
665 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
666 #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
667
668 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
669 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
670
671 /* Debug Core Register Selector Register */
672 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
673 #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
674
675 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
676 #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
677
678 /* Debug Exception and Monitor Control Register */
679 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
680 #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
681
682 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
683 #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
684
685 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
686 #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
687
688 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
689 #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
690
691 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
692 #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
693
694 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
695 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
696
697 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
698 #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
699
700 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
701 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
702
703 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
704 #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
705
706 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
707 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
708
709 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
710 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
711
712 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
713 #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
714
715 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
716 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
717 /*@}*/ /* end of group CMSIS_CM3_CoreDebug */
718
719
720 /* Memory mapping of Cortex-M3 Hardware */
721 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
722 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */
723 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
724 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
725 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
726 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
727
728 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
729 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
730 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
731 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
732 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
733 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
734
735 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
736 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
737 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
738 #endif
739
740 /*@}*/ /* end of group CMSIS_CM3_core_register */
741
742
743 /*******************************************************************************
744 * Hardware Abstraction Layer
745 ******************************************************************************/
746
747 #if defined ( __CC_ARM )
748 #define __ASM __asm /*!< asm keyword for ARM Compiler */
749 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
750
751 #elif defined ( __ICCARM__ )
752 #define __ASM __asm /*!< asm keyword for IAR Compiler */
753 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
754
755 #elif defined ( __GNUC__ )
756 #define __ASM __asm /*!< asm keyword for GNU Compiler */
757 #define __INLINE inline /*!< inline keyword for GNU Compiler */
758
759 #elif defined ( __TASKING__ )
760 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
761 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
762
763 #endif
764
765
766 /* ################### Compiler specific Intrinsics ########################### */
767
768 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
769 /* ARM armcc specific functions */
770
771 #define __enable_fault_irq __enable_fiq
772 #define __disable_fault_irq __disable_fiq
773
774 #define __NOP __nop
775 #define __WFI __wfi
776 #define __WFE __wfe
777 #define __SEV __sev
778 #define __ISB() __isb(0)
779 #define __DSB() __dsb(0)
780 #define __DMB() __dmb(0)
781 #define __REV __rev
782 #define __RBIT __rbit
783 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
784 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
785 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
786 #define __STREXB(value, ptr) __strex(value, ptr)
787 #define __STREXH(value, ptr) __strex(value, ptr)
788 #define __STREXW(value, ptr) __strex(value, ptr)
789
790
791 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
792 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
793 /* intrinsic void __enable_irq(); */
794 /* intrinsic void __disable_irq(); */
795
796
797 /**
798 * @brief Return the Process Stack Pointer
799 *
800 * @return ProcessStackPointer
801 *
802 * Return the actual process stack pointer
803 */
804 extern uint32_t __get_PSP(void);
805
806 /**
807 * @brief Set the Process Stack Pointer
808 *
809 * @param topOfProcStack Process Stack Pointer
810 *
811 * Assign the value ProcessStackPointer to the MSP
812 * (process stack pointer) Cortex processor register
813 */
814 extern void __set_PSP(uint32_t topOfProcStack);
815
816 /**
817 * @brief Return the Main Stack Pointer
818 *
819 * @return Main Stack Pointer
820 *
821 * Return the current value of the MSP (main stack pointer)
822 * Cortex processor register
823 */
824 extern uint32_t __get_MSP(void);
825
826 /**
827 * @brief Set the Main Stack Pointer
828 *
829 * @param topOfMainStack Main Stack Pointer
830 *
831 * Assign the value mainStackPointer to the MSP
832 * (main stack pointer) Cortex processor register
833 */
834 extern void __set_MSP(uint32_t topOfMainStack);
835
836 /**
837 * @brief Reverse byte order in unsigned short value
838 *
839 * @param value value to reverse
840 * @return reversed value
841 *
842 * Reverse byte order in unsigned short value
843 */
844 extern uint32_t __REV16(uint16_t value);
845
846 /**
847 * @brief Reverse byte order in signed short value with sign extension to integer
848 *
849 * @param value value to reverse
850 * @return reversed value
851 *
852 * Reverse byte order in signed short value with sign extension to integer
853 */
854 extern int32_t __REVSH(int16_t value);
855
856
857 #if (__ARMCC_VERSION < 400000)
858
859 /**
860 * @brief Remove the exclusive lock created by ldrex
861 *
862 * Removes the exclusive lock which is created by ldrex.
863 */
864 extern void __CLREX(void);
865
866 /**
867 * @brief Return the Base Priority value
868 *
869 * @return BasePriority
870 *
871 * Return the content of the base priority register
872 */
873 extern uint32_t __get_BASEPRI(void);
874
875 /**
876 * @brief Set the Base Priority value
877 *
878 * @param basePri BasePriority
879 *
880 * Set the base priority register
881 */
882 extern void __set_BASEPRI(uint32_t basePri);
883
884 /**
885 * @brief Return the Priority Mask value
886 *
887 * @return PriMask
888 *
889 * Return state of the priority mask bit from the priority mask register
890 */
891 extern uint32_t __get_PRIMASK(void);
892
893 /**
894 * @brief Set the Priority Mask value
895 *
896 * @param priMask PriMask
897 *
898 * Set the priority mask bit in the priority mask register
899 */
900 extern void __set_PRIMASK(uint32_t priMask);
901
902 /**
903 * @brief Return the Fault Mask value
904 *
905 * @return FaultMask
906 *
907 * Return the content of the fault mask register
908 */
909 extern uint32_t __get_FAULTMASK(void);
910
911 /**
912 * @brief Set the Fault Mask value
913 *
914 * @param faultMask faultMask value
915 *
916 * Set the fault mask register
917 */
918 extern void __set_FAULTMASK(uint32_t faultMask);
919
920 /**
921 * @brief Return the Control Register value
922 *
923 * @return Control value
924 *
925 * Return the content of the control register
926 */
927 extern uint32_t __get_CONTROL(void);
928
929 /**
930 * @brief Set the Control Register value
931 *
932 * @param control Control value
933 *
934 * Set the control register
935 */
936 extern void __set_CONTROL(uint32_t control);
937
938 #else /* (__ARMCC_VERSION >= 400000) */
939
940 /**
941 * @brief Remove the exclusive lock created by ldrex
942 *
943 * Removes the exclusive lock which is created by ldrex.
944 */
945 #define __CLREX __clrex
946
947 /**
948 * @brief Return the Base Priority value
949 *
950 * @return BasePriority
951 *
952 * Return the content of the base priority register
953 */
__get_BASEPRI(void)954 static __INLINE uint32_t __get_BASEPRI(void)
955 {
956 register uint32_t __regBasePri __ASM("basepri");
957 return(__regBasePri);
958 }
959
960 /**
961 * @brief Set the Base Priority value
962 *
963 * @param basePri BasePriority
964 *
965 * Set the base priority register
966 */
__set_BASEPRI(uint32_t basePri)967 static __INLINE void __set_BASEPRI(uint32_t basePri)
968 {
969 register uint32_t __regBasePri __ASM("basepri");
970 __regBasePri = (basePri & 0xff);
971 }
972
973 /**
974 * @brief Return the Priority Mask value
975 *
976 * @return PriMask
977 *
978 * Return state of the priority mask bit from the priority mask register
979 */
__get_PRIMASK(void)980 static __INLINE uint32_t __get_PRIMASK(void)
981 {
982 register uint32_t __regPriMask __ASM("primask");
983 return(__regPriMask);
984 }
985
986 /**
987 * @brief Set the Priority Mask value
988 *
989 * @param priMask PriMask
990 *
991 * Set the priority mask bit in the priority mask register
992 */
__set_PRIMASK(uint32_t priMask)993 static __INLINE void __set_PRIMASK(uint32_t priMask)
994 {
995 register uint32_t __regPriMask __ASM("primask");
996 __regPriMask = (priMask);
997 }
998
999 /**
1000 * @brief Return the Fault Mask value
1001 *
1002 * @return FaultMask
1003 *
1004 * Return the content of the fault mask register
1005 */
__get_FAULTMASK(void)1006 static __INLINE uint32_t __get_FAULTMASK(void)
1007 {
1008 register uint32_t __regFaultMask __ASM("faultmask");
1009 return(__regFaultMask);
1010 }
1011
1012 /**
1013 * @brief Set the Fault Mask value
1014 *
1015 * @param faultMask faultMask value
1016 *
1017 * Set the fault mask register
1018 */
__set_FAULTMASK(uint32_t faultMask)1019 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
1020 {
1021 register uint32_t __regFaultMask __ASM("faultmask");
1022 __regFaultMask = (faultMask & 1);
1023 }
1024
1025 /**
1026 * @brief Return the Control Register value
1027 *
1028 * @return Control value
1029 *
1030 * Return the content of the control register
1031 */
__get_CONTROL(void)1032 static __INLINE uint32_t __get_CONTROL(void)
1033 {
1034 register uint32_t __regControl __ASM("control");
1035 return(__regControl);
1036 }
1037
1038 /**
1039 * @brief Set the Control Register value
1040 *
1041 * @param control Control value
1042 *
1043 * Set the control register
1044 */
__set_CONTROL(uint32_t control)1045 static __INLINE void __set_CONTROL(uint32_t control)
1046 {
1047 register uint32_t __regControl __ASM("control");
1048 __regControl = control;
1049 }
1050
1051 #endif /* __ARMCC_VERSION */
1052
1053
1054
1055 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
1056 /* IAR iccarm specific functions */
1057
1058 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
1059 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
1060
__enable_fault_irq()1061 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
__disable_fault_irq()1062 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
1063
1064 #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
__WFI()1065 static __INLINE void __WFI() { __ASM ("wfi"); }
__WFE()1066 static __INLINE void __WFE() { __ASM ("wfe"); }
__SEV()1067 static __INLINE void __SEV() { __ASM ("sev"); }
__CLREX()1068 static __INLINE void __CLREX() { __ASM ("clrex"); }
1069
1070 /* intrinsic void __ISB(void) */
1071 /* intrinsic void __DSB(void) */
1072 /* intrinsic void __DMB(void) */
1073 /* intrinsic void __set_PRIMASK(); */
1074 /* intrinsic void __get_PRIMASK(); */
1075 /* intrinsic void __set_FAULTMASK(); */
1076 /* intrinsic void __get_FAULTMASK(); */
1077 /* intrinsic uint32_t __REV(uint32_t value); */
1078 /* intrinsic uint32_t __REVSH(uint32_t value); */
1079 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
1080 /* intrinsic unsigned long __LDREX(unsigned long *); */
1081
1082
1083 /**
1084 * @brief Return the Process Stack Pointer
1085 *
1086 * @return ProcessStackPointer
1087 *
1088 * Return the actual process stack pointer
1089 */
1090 #if (__VER__ < 6020000)
1091 extern uint32_t __get_PSP(void);
1092 #endif
1093
1094 /**
1095 * @brief Set the Process Stack Pointer
1096 *
1097 * @param topOfProcStack Process Stack Pointer
1098 *
1099 * Assign the value ProcessStackPointer to the MSP
1100 * (process stack pointer) Cortex processor register
1101 */
1102 #if (__VER__ < 6020000)
1103 extern void __set_PSP(uint32_t topOfProcStack);
1104 #endif
1105
1106 /**
1107 * @brief Return the Main Stack Pointer
1108 *
1109 * @return Main Stack Pointer
1110 *
1111 * Return the current value of the MSP (main stack pointer)
1112 * Cortex processor register
1113 */
1114 #if (__VER__ < 6020000)
1115 extern uint32_t __get_MSP(void);
1116 #endif
1117
1118 /**
1119 * @brief Set the Main Stack Pointer
1120 *
1121 * @param topOfMainStack Main Stack Pointer
1122 *
1123 * Assign the value mainStackPointer to the MSP
1124 * (main stack pointer) Cortex processor register
1125 */
1126 #if (__VER__ < 6020000)
1127 extern void __set_MSP(uint32_t topOfMainStack);
1128 #endif
1129
1130 /**
1131 * @brief Reverse byte order in unsigned short value
1132 *
1133 * @param value value to reverse
1134 * @return reversed value
1135 *
1136 * Reverse byte order in unsigned short value
1137 */
1138 #if (__VER__ < 6020000)
1139 extern uint32_t __REV16(uint16_t value);
1140 #endif
1141
1142 /**
1143 * @brief Reverse bit order of value
1144 *
1145 * @param value value to reverse
1146 * @return reversed value
1147 *
1148 * Reverse bit order of value
1149 */
1150 #if (__VER__ < 6020000)
1151 extern uint32_t __RBIT(uint32_t value);
1152 #endif
1153
1154 /**
1155 * @brief LDR Exclusive (8 bit)
1156 *
1157 * @param *addr address pointer
1158 * @return value of (*address)
1159 *
1160 * Exclusive LDR command for 8 bit values)
1161 */
1162 #if (__VER__ < 6020000)
1163 extern uint8_t __LDREXB(uint8_t *addr);
1164 #endif
1165
1166 /**
1167 * @brief LDR Exclusive (16 bit)
1168 *
1169 * @param *addr address pointer
1170 * @return value of (*address)
1171 *
1172 * Exclusive LDR command for 16 bit values
1173 */
1174 #if (__VER__ < 6020000)
1175 extern uint16_t __LDREXH(uint16_t *addr);
1176 #endif
1177
1178 /**
1179 * @brief LDR Exclusive (32 bit)
1180 *
1181 * @param *addr address pointer
1182 * @return value of (*address)
1183 *
1184 * Exclusive LDR command for 32 bit values
1185 */
1186 extern uint32_t __LDREXW(uint32_t *addr);
1187
1188 /**
1189 * @brief STR Exclusive (8 bit)
1190 *
1191 * @param value value to store
1192 * @param *addr address pointer
1193 * @return successful / failed
1194 *
1195 * Exclusive STR command for 8 bit values
1196 */
1197 #if (__VER__ < 6020000)
1198 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1199 #endif
1200
1201 /**
1202 * @brief STR Exclusive (16 bit)
1203 *
1204 * @param value value to store
1205 * @param *addr address pointer
1206 * @return successful / failed
1207 *
1208 * Exclusive STR command for 16 bit values
1209 */
1210 #if (__VER__ < 6020000)
1211 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1212 #endif
1213
1214 /**
1215 * @brief STR Exclusive (32 bit)
1216 *
1217 * @param value value to store
1218 * @param *addr address pointer
1219 * @return successful / failed
1220 *
1221 * Exclusive STR command for 32 bit values
1222 */
1223 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1224
1225
1226
1227 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
1228 /* GNU gcc specific functions */
1229
__enable_irq(void)1230 static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }
__disable_irq(void)1231 static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }
1232
__enable_fault_irq(void)1233 static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }
__disable_fault_irq(void)1234 static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }
1235
__NOP(void)1236 static __INLINE void __NOP(void) { __ASM volatile ("nop"); }
__WFI(void)1237 static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }
__WFE(void)1238 static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }
__SEV(void)1239 static __INLINE void __SEV(void) { __ASM volatile ("sev"); }
__ISB(void)1240 static __INLINE void __ISB(void) { __ASM volatile ("isb"); }
__DSB(void)1241 static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }
__DMB(void)1242 static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }
__CLREX(void)1243 static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); }
1244
1245
1246 /**
1247 * @brief Return the Process Stack Pointer
1248 *
1249 * @return ProcessStackPointer
1250 *
1251 * Return the actual process stack pointer
1252 */
1253 extern uint32_t __get_PSP(void);
1254
1255 /**
1256 * @brief Set the Process Stack Pointer
1257 *
1258 * @param topOfProcStack Process Stack Pointer
1259 *
1260 * Assign the value ProcessStackPointer to the MSP
1261 * (process stack pointer) Cortex processor register
1262 */
1263 extern void __set_PSP(uint32_t topOfProcStack);
1264
1265 /**
1266 * @brief Return the Main Stack Pointer
1267 *
1268 * @return Main Stack Pointer
1269 *
1270 * Return the current value of the MSP (main stack pointer)
1271 * Cortex processor register
1272 */
1273 extern uint32_t __get_MSP(void);
1274
1275 /**
1276 * @brief Set the Main Stack Pointer
1277 *
1278 * @param topOfMainStack Main Stack Pointer
1279 *
1280 * Assign the value mainStackPointer to the MSP
1281 * (main stack pointer) Cortex processor register
1282 */
1283 extern void __set_MSP(uint32_t topOfMainStack);
1284
1285 /**
1286 * @brief Return the Base Priority value
1287 *
1288 * @return BasePriority
1289 *
1290 * Return the content of the base priority register
1291 */
1292 extern uint32_t __get_BASEPRI(void);
1293
1294 /**
1295 * @brief Set the Base Priority value
1296 *
1297 * @param basePri BasePriority
1298 *
1299 * Set the base priority register
1300 */
1301 extern void __set_BASEPRI(uint32_t basePri);
1302
1303 /**
1304 * @brief Return the Priority Mask value
1305 *
1306 * @return PriMask
1307 *
1308 * Return state of the priority mask bit from the priority mask register
1309 */
1310 extern uint32_t __get_PRIMASK(void);
1311
1312 /**
1313 * @brief Set the Priority Mask value
1314 *
1315 * @param priMask PriMask
1316 *
1317 * Set the priority mask bit in the priority mask register
1318 */
1319 extern void __set_PRIMASK(uint32_t priMask);
1320
1321 /**
1322 * @brief Return the Fault Mask value
1323 *
1324 * @return FaultMask
1325 *
1326 * Return the content of the fault mask register
1327 */
1328 extern uint32_t __get_FAULTMASK(void);
1329
1330 /**
1331 * @brief Set the Fault Mask value
1332 *
1333 * @param faultMask faultMask value
1334 *
1335 * Set the fault mask register
1336 */
1337 extern void __set_FAULTMASK(uint32_t faultMask);
1338
1339 /**
1340 * @brief Return the Control Register value
1341 *
1342 * @return Control value
1343 *
1344 * Return the content of the control register
1345 */
1346 extern uint32_t __get_CONTROL(void);
1347
1348 /**
1349 * @brief Set the Control Register value
1350 *
1351 * @param control Control value
1352 *
1353 * Set the control register
1354 */
1355 extern void __set_CONTROL(uint32_t control);
1356
1357 /**
1358 * @brief Reverse byte order in integer value
1359 *
1360 * @param value value to reverse
1361 * @return reversed value
1362 *
1363 * Reverse byte order in integer value
1364 */
1365 extern uint32_t __REV(uint32_t value);
1366
1367 /**
1368 * @brief Reverse byte order in unsigned short value
1369 *
1370 * @param value value to reverse
1371 * @return reversed value
1372 *
1373 * Reverse byte order in unsigned short value
1374 */
1375 extern uint32_t __REV16(uint16_t value);
1376
1377 /**
1378 * @brief Reverse byte order in signed short value with sign extension to integer
1379 *
1380 * @param value value to reverse
1381 * @return reversed value
1382 *
1383 * Reverse byte order in signed short value with sign extension to integer
1384 */
1385 extern int32_t __REVSH(int16_t value);
1386
1387 /**
1388 * @brief Reverse bit order of value
1389 *
1390 * @param value value to reverse
1391 * @return reversed value
1392 *
1393 * Reverse bit order of value
1394 */
1395 extern uint32_t __RBIT(uint32_t value);
1396
1397 /**
1398 * @brief LDR Exclusive (8 bit)
1399 *
1400 * @param *addr address pointer
1401 * @return value of (*address)
1402 *
1403 * Exclusive LDR command for 8 bit value
1404 */
1405 extern uint8_t __LDREXB(uint8_t *addr);
1406
1407 /**
1408 * @brief LDR Exclusive (16 bit)
1409 *
1410 * @param *addr address pointer
1411 * @return value of (*address)
1412 *
1413 * Exclusive LDR command for 16 bit values
1414 */
1415 extern uint16_t __LDREXH(uint16_t *addr);
1416
1417 /**
1418 * @brief LDR Exclusive (32 bit)
1419 *
1420 * @param *addr address pointer
1421 * @return value of (*address)
1422 *
1423 * Exclusive LDR command for 32 bit values
1424 */
1425 extern uint32_t __LDREXW(uint32_t *addr);
1426
1427 /**
1428 * @brief STR Exclusive (8 bit)
1429 *
1430 * @param value value to store
1431 * @param *addr address pointer
1432 * @return successful / failed
1433 *
1434 * Exclusive STR command for 8 bit values
1435 */
1436 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1437
1438 /**
1439 * @brief STR Exclusive (16 bit)
1440 *
1441 * @param value value to store
1442 * @param *addr address pointer
1443 * @return successful / failed
1444 *
1445 * Exclusive STR command for 16 bit values
1446 */
1447 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1448
1449 /**
1450 * @brief STR Exclusive (32 bit)
1451 *
1452 * @param value value to store
1453 * @param *addr address pointer
1454 * @return successful / failed
1455 *
1456 * Exclusive STR command for 32 bit values
1457 */
1458 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1459
1460
1461 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
1462 /* TASKING carm specific functions */
1463
1464 /*
1465 * The CMSIS functions have been implemented as intrinsics in the compiler.
1466 * Please use "carm -?i" to get an up to date list of all instrinsics,
1467 * Including the CMSIS ones.
1468 */
1469
1470 #endif
1471
1472
1473 /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
1474 Core Function Interface containing:
1475 - Core NVIC Functions
1476 - Core SysTick Functions
1477 - Core Reset Functions
1478 */
1479 /*@{*/
1480
1481 /* ########################## NVIC functions #################################### */
1482
1483 /**
1484 * @brief Set the Priority Grouping in NVIC Interrupt Controller
1485 *
1486 * @param PriorityGroup is priority grouping field
1487 *
1488 * Set the priority grouping field using the required unlock sequence.
1489 * The parameter priority_grouping is assigned to the field
1490 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
1491 * In case of a conflict between priority grouping and available
1492 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1493 */
NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1494 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1495 {
1496 uint32_t reg_value;
1497 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1498
1499 reg_value = SCB->AIRCR; /* read old register configuration */
1500 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1501 reg_value = (reg_value |
1502 (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1503 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1504 SCB->AIRCR = reg_value;
1505 }
1506
1507 /**
1508 * @brief Get the Priority Grouping from NVIC Interrupt Controller
1509 *
1510 * @return priority grouping field
1511 *
1512 * Get the priority grouping from NVIC Interrupt Controller.
1513 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
1514 */
NVIC_GetPriorityGrouping(void)1515 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
1516 {
1517 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1518 }
1519
1520 /**
1521 * @brief Enable Interrupt in NVIC Interrupt Controller
1522 *
1523 * @param IRQn The positive number of the external interrupt to enable
1524 *
1525 * Enable a device specific interupt in the NVIC interrupt controller.
1526 * The interrupt number cannot be a negative value.
1527 */
NVIC_EnableIRQ(IRQn_Type IRQn)1528 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1529 {
1530 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1531 }
1532
1533 /**
1534 * @brief Disable the interrupt line for external interrupt specified
1535 *
1536 * @param IRQn The positive number of the external interrupt to disable
1537 *
1538 * Disable a device specific interupt in the NVIC interrupt controller.
1539 * The interrupt number cannot be a negative value.
1540 */
NVIC_DisableIRQ(IRQn_Type IRQn)1541 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1542 {
1543 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1544 }
1545
1546 /**
1547 * @brief Read the interrupt pending bit for a device specific interrupt source
1548 *
1549 * @param IRQn The number of the device specifc interrupt
1550 * @return 1 = interrupt pending, 0 = interrupt not pending
1551 *
1552 * Read the pending register in NVIC and return 1 if its status is pending,
1553 * otherwise it returns 0
1554 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)1555 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1556 {
1557 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1558 }
1559
1560 /**
1561 * @brief Set the pending bit for an external interrupt
1562 *
1563 * @param IRQn The number of the interrupt for set pending
1564 *
1565 * Set the pending bit for the specified interrupt.
1566 * The interrupt number cannot be a negative value.
1567 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)1568 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1569 {
1570 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1571 }
1572
1573 /**
1574 * @brief Clear the pending bit for an external interrupt
1575 *
1576 * @param IRQn The number of the interrupt for clear pending
1577 *
1578 * Clear the pending bit for the specified interrupt.
1579 * The interrupt number cannot be a negative value.
1580 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)1581 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1582 {
1583 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1584 }
1585
1586 /**
1587 * @brief Read the active bit for an external interrupt
1588 *
1589 * @param IRQn The number of the interrupt for read active bit
1590 * @return 1 = interrupt active, 0 = interrupt not active
1591 *
1592 * Read the active register in NVIC and returns 1 if its status is active,
1593 * otherwise it returns 0.
1594 */
NVIC_GetActive(IRQn_Type IRQn)1595 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1596 {
1597 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1598 }
1599
1600 /**
1601 * @brief Set the priority for an interrupt
1602 *
1603 * @param IRQn The number of the interrupt for set priority
1604 * @param priority The priority to set
1605 *
1606 * Set the priority for the specified interrupt. The interrupt
1607 * number can be positive to specify an external (device specific)
1608 * interrupt, or negative to specify an internal (core) interrupt.
1609 *
1610 * Note: The priority cannot be set for every core interrupt.
1611 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1612 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1613 {
1614 if(IRQn < 0) {
1615 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
1616 else {
1617 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1618 }
1619
1620 /**
1621 * @brief Read the priority for an interrupt
1622 *
1623 * @param IRQn The number of the interrupt for get priority
1624 * @return The priority for the interrupt
1625 *
1626 * Read the priority for the specified interrupt. The interrupt
1627 * number can be positive to specify an external (device specific)
1628 * interrupt, or negative to specify an internal (core) interrupt.
1629 *
1630 * The returned priority value is automatically aligned to the implemented
1631 * priority bits of the microcontroller.
1632 *
1633 * Note: The priority cannot be set for every core interrupt.
1634 */
NVIC_GetPriority(IRQn_Type IRQn)1635 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1636 {
1637
1638 if(IRQn < 0) {
1639 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
1640 else {
1641 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1642 }
1643
1644
1645 /**
1646 * @brief Encode the priority for an interrupt
1647 *
1648 * @param PriorityGroup The used priority group
1649 * @param PreemptPriority The preemptive priority value (starting from 0)
1650 * @param SubPriority The sub priority value (starting from 0)
1651 * @return The encoded priority for the interrupt
1652 *
1653 * Encode the priority for an interrupt with the given priority group,
1654 * preemptive priority value and sub priority value.
1655 * In case of a conflict between priority grouping and available
1656 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1657 *
1658 * The returned priority value can be used for NVIC_SetPriority(...) function
1659 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1660 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1661 {
1662 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1663 uint32_t PreemptPriorityBits;
1664 uint32_t SubPriorityBits;
1665
1666 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1667 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1668
1669 return (
1670 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1671 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1672 );
1673 }
1674
1675
1676 /**
1677 * @brief Decode the priority of an interrupt
1678 *
1679 * @param Priority The priority for the interrupt
1680 * @param PriorityGroup The used priority group
1681 * @param pPreemptPriority The preemptive priority value (starting from 0)
1682 * @param pSubPriority The sub priority value (starting from 0)
1683 *
1684 * Decode an interrupt priority value with the given priority group to
1685 * preemptive priority value and sub priority value.
1686 * In case of a conflict between priority grouping and available
1687 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1688 *
1689 * The priority value can be retrieved with NVIC_GetPriority(...) function
1690 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)1691 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1692 {
1693 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1694 uint32_t PreemptPriorityBits;
1695 uint32_t SubPriorityBits;
1696
1697 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1698 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1699
1700 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1701 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1702 }
1703
1704
1705
1706 /* ################################## SysTick function ############################################ */
1707
1708 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
1709
1710 /**
1711 * @brief Initialize and start the SysTick counter and its interrupt.
1712 *
1713 * @param ticks number of ticks between two interrupts
1714 * @return 1 = failed, 0 = successful
1715 *
1716 * Initialise the system tick timer and its interrupt and start the
1717 * system tick timer / counter in free running mode to generate
1718 * periodical interrupts.
1719 */
SysTick_Config(uint32_t ticks)1720 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1721 {
1722 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1723
1724 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1725 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
1726 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1727 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1728 SysTick_CTRL_TICKINT_Msk |
1729 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1730 return (0); /* Function successful */
1731 }
1732
1733 #endif
1734
1735
1736
1737
1738 /* ################################## Reset function ############################################ */
1739
1740 /**
1741 * @brief Initiate a system reset request.
1742 *
1743 * Initiate a system reset request to reset the MCU
1744 */
NVIC_SystemReset(void)1745 static __INLINE void NVIC_SystemReset(void)
1746 {
1747 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1748 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1749 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1750 __DSB(); /* Ensure completion of memory access */
1751 while(1); /* wait until reset */
1752 }
1753
1754 /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
1755
1756
1757
1758 /* ##################################### Debug In/Output function ########################################### */
1759
1760 /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
1761 Core Debug Interface containing:
1762 - Core Debug Receive / Transmit Functions
1763 - Core Debug Defines
1764 - Core Debug Variables
1765 */
1766 /*@{*/
1767
1768 extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
1769 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
1770
1771
1772 /**
1773 * @brief Outputs a character via the ITM channel 0
1774 *
1775 * @param ch character to output
1776 * @return character to output
1777 *
1778 * The function outputs a character via the ITM channel 0.
1779 * The function returns when no debugger is connected that has booked the output.
1780 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1781 */
ITM_SendChar(uint32_t ch)1782 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1783 {
1784 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
1785 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1786 (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
1787 {
1788 while (ITM->PORT[0].u32 == 0);
1789 ITM->PORT[0].u8 = (uint8_t) ch;
1790 }
1791 return (ch);
1792 }
1793
1794
1795 /**
1796 * @brief Inputs a character via variable ITM_RxBuffer
1797 *
1798 * @return received character, -1 = no character received
1799 *
1800 * The function inputs a character via variable ITM_RxBuffer.
1801 * The function returns when no debugger is connected that has booked the output.
1802 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1803 */
ITM_ReceiveChar(void)1804 static __INLINE int ITM_ReceiveChar (void) {
1805 int ch = -1; /* no character available */
1806
1807 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1808 ch = ITM_RxBuffer;
1809 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1810 }
1811
1812 return (ch);
1813 }
1814
1815
1816 /**
1817 * @brief Check if a character via variable ITM_RxBuffer is available
1818 *
1819 * @return 1 = character available, 0 = no character available
1820 *
1821 * The function checks variable ITM_RxBuffer whether a character is available or not.
1822 * The function returns '1' if a character is available and '0' if no character is available.
1823 */
ITM_CheckChar(void)1824 static __INLINE int ITM_CheckChar (void) {
1825
1826 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1827 return (0); /* no character available */
1828 } else {
1829 return (1); /* character available */
1830 }
1831 }
1832
1833 /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
1834
1835
1836 #ifdef __cplusplus
1837 }
1838 #endif
1839
1840 /*@}*/ /* end of group CMSIS_CM3_core_definitions */
1841
1842 #endif /* __CM3_CORE_H__ */
1843
1844 /*lint -restore */
1845