1 /*=============================================================*/
2 /* Created by Microsemi SmartDesign Fri May 22 15:04:18 2020   */
3 /*                                                             */
4 /* Warning: Do not modify this file, it may lead to unexpected */
5 /*          functional failures in your design.                */
6 /*                                                             */
7 /*=============================================================*/
8 
9 #ifndef SYS_CONFIG_MSS_CLOCKS
10 #define SYS_CONFIG_MSS_CLOCKS
11 
12 #define MSS_SYS_M3_CLK_FREQ             100000000u
13 #define MSS_SYS_MDDR_CLK_FREQ           100000000u
14 #define MSS_SYS_APB_0_CLK_FREQ          100000000u
15 #define MSS_SYS_APB_1_CLK_FREQ          100000000u
16 #define MSS_SYS_APB_2_CLK_FREQ          25000000u
17 #define MSS_SYS_FIC_0_CLK_FREQ          100000000u
18 #define MSS_SYS_FIC_1_CLK_FREQ          100000000u
19 #define MSS_SYS_FIC64_CLK_FREQ          100000000u
20 
21 #endif /* SYS_CONFIG_MSS_CLOCKS */
22