1 // See LICENSE for license details.
2 
3 #ifndef _SIFIVE_COREPLEXIP_ARTY_H
4 #define _SIFIVE_COREPLEXIP_ARTY_H
5 
6 #include <stdint.h>
7 
8 /****************************************************************************
9  * GPIO Connections
10  *****************************************************************************/
11 
12 // These are the GPIO bit offsets for the directly driven
13 // RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit.
14 // Additional RGB LEDs are driven by the 3 PWM outputs.
15 
16 #define RED_LED_OFFSET   0
17 #define GREEN_LED_OFFSET 1
18 #define BLUE_LED_OFFSET  2
19 
20 // Switch 3 is used as a GPIO input. (Switch 0 is used to set
21 // the reset vector, the other switches are unused).
22 
23 #define SW_3_OFFSET      3
24 
25 // These are the buttons which are mapped as inputs.
26 
27 #define HAS_BOARD_BUTTONS
28 
29 #define BUTTON_0_OFFSET  4
30 #define BUTTON_1_OFFSET  5
31 #define BUTTON_2_OFFSET  6
32 #define BUTTON_3_OFFSET  7
33 
34 // These are the bit offsets for the different GPIO pins
35 // mapped onto the PMOD A header.
36 
37 #define JA_0_OFFSET 8
38 #define JA_1_OFFSET 9
39 #define JA_2_OFFSET 10
40 #define JA_3_OFFSET 11
41 #define JA_4_OFFSET 12
42 #define JA_5_OFFSET 13
43 #define JA_6_OFFSET 14
44 #define JA_7_OFFSET 15
45 
46 // The below gives a mapping between global interrupt
47 // sources and their number. Note that on the coreplex
48 // deliverable, the io_global_interrupts go directly into
49 // the PLIC. The evaluation image on the FPGA mimics a
50 // system with peripheral devices which are driving the
51 // global interrupt lines.
52 // So, on this image, in order to get an interrupt from
53 // e.g. pressing BUTTON_0:
54 // 1) Steps which are external to the delivery coreplex:
55 //   a) The corresponding GPIO pin must be configured as in input
56 //   b) The "interrupt on fall" bit must be set for the GPIO pin
57 // 2) Steps which would also need to be performed for the delivery coreplex:
58 //   a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC.
59 //   b) The external interrupt bit must be enabled in MSTATUS
60 //   c) Interrupts must be enabled globally in the core.
61 
62 // Any of the above GPIO pins can be used as global interrupt
63 // sources by adding their offset to the INT_GPIO_BASE.
64 // For example, the buttons are shown here:
65 
66 #define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET)
67 #define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET)
68 #define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET)
69 #define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET)
70 
71 // In addition, the Switches are mapped directly to
72 // the PLIC (without going through the GPIO Peripheral).
73 
74 #define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0)
75 #define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1)
76 #define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2)
77 #define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3)
78 
79 // This gives the mapping from inputs to LOCAL interrupts.
80 
81 #define LOCAL_INT_SW_0   0
82 #define LOCAL_INT_SW_1   1
83 #define LOCAL_INT_SW_2   2
84 #define LOCAL_INT_SW_3   3
85 #define LOCAL_INT_BTN_0  4
86 #define LOCAL_INT_BTN_1  5
87 #define LOCAL_INT_BTN_2  6
88 #define LOCAL_INT_BTN_3  7
89 #define LOCAL_INT_JA_0   8
90 #define LOCAL_INT_JA_1   9
91 #define LOCAL_INT_JA_2   10
92 #define LOCAL_INT_JA_3   11
93 #define LOCAL_INT_JA_4   12
94 #define LOCAL_INT_JA_5   13
95 #define LOCAL_INT_JA_6   14
96 #define LOCAL_INT_JA_7   15
97 
98 #define RTC_FREQ 32768
99 
100 void write_hex(int fd, unsigned long int hex);
101 
102 #endif /* _SIFIVE_COREPLEXIP_ARTY_H */
103