1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-01-02 SummerGift first version 9 * 2019-01-08 SummerGift clean up the code 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 channel1 */ 22 #if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE) 23 #define ADC1_DMA_IRQHandler DMA1_Channel1_IRQHandler 24 #define ADC1_DMA_RCC RCC_AHBENR_DMA1EN 25 #define ADC1_DMA_INSTANCE DMA1_Channel1 26 #define ADC1_DMA_IRQ DMA1_Channel1_IRQn 27 #endif 28 29 /* DMA1 channel2 */ 30 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 31 #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler 32 #define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN 33 #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 34 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn 35 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) 36 #define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler 37 #define UART3_TX_DMA_RCC RCC_AHBENR_DMA1EN 38 #define UART3_TX_DMA_INSTANCE DMA1_Channel2 39 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn 40 #endif 41 42 /* DMA1 channel3 */ 43 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 44 #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler 45 #define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN 46 #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 47 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn 48 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 49 #define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler 50 #define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN 51 #define UART3_RX_DMA_INSTANCE DMA1_Channel3 52 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn 53 #endif 54 55 /* DMA1 channel4 */ 56 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 57 #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler 58 #define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN 59 #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 60 #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn 61 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 62 #define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler 63 #define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN 64 #define UART1_TX_DMA_INSTANCE DMA1_Channel4 65 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn 66 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) 67 #define I2C2_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler 68 #define I2C2_TX_DMA_RCC RCC_AHBENR_DMA1EN 69 #define I2C2_TX_DMA_INSTANCE DMA1_Channel4 70 #define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn 71 #endif 72 73 /* DMA1 channel5 */ 74 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 75 #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler 76 #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN 77 #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 78 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn 79 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 80 #define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler 81 #define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN 82 #define UART1_RX_DMA_INSTANCE DMA1_Channel5 83 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn 84 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) 85 #define I2C2_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler 86 #define I2C2_RX_DMA_RCC RCC_AHBENR_DMA1EN 87 #define I2C2_RX_DMA_INSTANCE DMA1_Channel5 88 #define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn 89 #endif 90 91 /* DMA1 channel6 */ 92 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 93 #define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler 94 #define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN 95 #define UART2_RX_DMA_INSTANCE DMA1_Channel6 96 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn 97 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) 98 #define I2C1_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler 99 #define I2C1_TX_DMA_RCC RCC_AHBENR_DMA1EN 100 #define I2C1_TX_DMA_INSTANCE DMA1_Channel6 101 #define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn 102 #endif 103 104 /* DMA1 channel7 */ 105 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 106 #define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler 107 #define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN 108 #define UART2_TX_DMA_INSTANCE DMA1_Channel7 109 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn 110 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) 111 #define I2C1_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler 112 #define I2C1_RX_DMA_RCC RCC_AHBENR_DMA1EN 113 #define I2C1_RX_DMA_INSTANCE DMA1_Channel7 114 #define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn 115 #endif 116 117 /* DMA2 channel1 */ 118 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 119 #define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler 120 #define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN 121 #define SPI3_RX_DMA_INSTANCE DMA2_Channel1 122 #define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn 123 #endif 124 125 /* DMA2 channel2 */ 126 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 127 #define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler 128 #define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN 129 #define SPI3_TX_DMA_INSTANCE DMA2_Channel2 130 #define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn 131 #endif 132 133 /* DMA2 channel3 */ 134 #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 135 #define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler 136 #define UART4_RX_DMA_RCC RCC_AHBENR_DMA2EN 137 #define UART4_RX_DMA_INSTANCE DMA2_Channel3 138 #define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn 139 #endif 140 141 /* DMA2 channel4 */ 142 #if defined(BSP_SDIO_TX_USING_DMA) && !defined(SDIO_TX_DMA_INSTANCE) 143 #define SDIO_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler 144 #define SDIO_TX_DMA_RCC RCC_AHBENR_DMA2EN 145 #define SDIO_TX_DMA_INSTANCE DMA2_Channel4 146 #define SDIO_TX_DMA_IRQ DMA2_Channel4_5_IRQn 147 #elif defined(BSP_SDIO_RX_USING_DMA) && !defined(SDIO_RX_DMA_INSTANCE) 148 #define SDIO_DMA_RX_IRQHandler DMA2_Channel4_5_IRQHandler 149 #define SDIO_RX_DMA_RCC RCC_AHBENR_DMA2EN 150 #define SDIO_RX_DMA_INSTANCE DMA2_Channel4 151 #define SDIO_RX_DMA_IRQ DMA2_Channel4_5_IRQn 152 #endif 153 154 /* DMA2 channel5 */ 155 #if defined(BSP_ADC3_USING_DMA) && !defined(ADC3_DMA_INSTANCE) 156 #define ADC3_DMA_IRQHandler DMA2_Channel4_5_IRQHandler 157 #define ADC3_DMA_RCC RCC_AHBENR_DMA2EN 158 #define ADC3_DMA_INSTANCE DMA2_Channel5 159 #define ADC3_DMA_IRQ DMA2_Channel4_5_IRQn 160 #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) 161 #define UART4_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler 162 #define UART4_TX_DMA_RCC RCC_AHBENR_DMA2EN 163 #define UART4_TX_DMA_INSTANCE DMA2_Channel5 164 #define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn 165 #endif 166 167 #ifdef __cplusplus 168 } 169 #endif 170 171 #endif /* __DMA_CONFIG_H__ */ 172