1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-01-02 zylx first version 9 * 2019-01-08 SummerGift clean up the code 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 stream0 */ 22 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 23 #define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 24 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 25 #define SPI3_RX_DMA_INSTANCE DMA1_Stream0 26 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 27 #define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn 28 #elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) 29 #define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 30 #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 31 #define UART5_RX_DMA_INSTANCE DMA1_Stream0 32 #define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 33 #define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn 34 #endif 35 36 /* DMA1 stream1 */ 37 #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 38 #define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler 39 #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 40 #define UART3_RX_DMA_INSTANCE DMA1_Stream1 41 #define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 42 #define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn 43 #endif 44 45 /* DMA1 stream2 */ 46 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 47 #define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 48 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 49 #define SPI3_RX_DMA_INSTANCE DMA1_Stream2 50 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 51 #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn 52 #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 53 #define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 54 #define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 55 #define UART4_RX_DMA_INSTANCE DMA1_Stream2 56 #define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 57 #define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn 58 #endif 59 60 /* DMA1 stream3 */ 61 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 62 #define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler 63 #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 64 #define SPI2_RX_DMA_INSTANCE DMA1_Stream3 65 #define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 66 #define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn 67 #endif 68 69 /* DMA1 stream4 */ 70 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 71 #define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler 72 #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 73 #define SPI2_TX_DMA_INSTANCE DMA1_Stream4 74 #define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 75 #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn 76 #endif 77 78 /* DMA1 stream5 */ 79 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 80 #define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler 81 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 82 #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 83 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 84 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn 85 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 86 #define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler 87 #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 88 #define UART2_RX_DMA_INSTANCE DMA1_Stream5 89 #define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 90 #define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn 91 #endif 92 93 /* DMA1 stream6 */ 94 95 /* DMA1 stream7 */ 96 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 97 #define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler 98 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 99 #define SPI3_TX_DMA_INSTANCE DMA1_Stream7 100 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 101 #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn 102 #endif 103 104 /* DMA2 stream0 */ 105 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 106 #define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler 107 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 108 #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 109 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 110 #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn 111 #endif 112 113 /* DMA2 stream1 */ 114 115 /* DMA2 stream2 */ 116 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 117 #define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 118 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 119 #define SPI1_RX_DMA_INSTANCE DMA2_Stream2 120 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 121 #define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn 122 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 123 #define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 124 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 125 #define UART1_RX_DMA_INSTANCE DMA2_Stream2 126 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 127 #define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn 128 #elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) 129 #define UART6_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 130 #define UART6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 131 #define UART6_RX_DMA_INSTANCE DMA2_Stream2 132 #define UART6_RX_DMA_CHANNEL DMA_CHANNEL_5 133 #define UART6_RX_DMA_IRQ DMA2_Stream2_IRQn 134 #endif 135 /* DMA2 stream3 */ 136 137 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 138 #define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler 139 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 140 #define SPI1_TX_DMA_INSTANCE DMA2_Stream3 141 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 142 #define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn 143 #endif 144 145 /* DMA2 stream4 */ 146 147 /* DMA2 stream5 */ 148 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 149 #define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler 150 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 151 #define SPI1_TX_DMA_INSTANCE DMA2_Stream5 152 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 153 #define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn 154 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 155 #define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler 156 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 157 #define UART1_RX_DMA_INSTANCE DMA2_Stream5 158 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 159 #define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn 160 #endif 161 162 /* DMA2 stream6 */ 163 164 /* DMA2 stream7 */ 165 166 #ifdef __cplusplus 167 } 168 #endif 169 170 171 #endif /* __DMA_CONFIG_H__ */ 172