1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-02-06 Dyyt587 first version 9 * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG 10 */ 11 #ifndef __I2C_HARD_CONFIG_H__ 12 #define __I2C_HARD_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #ifdef BSP_USING_HARD_I2C1 21 #ifndef I2C1_BUS_CONFIG 22 #define I2C1_BUS_CONFIG \ 23 { \ 24 .Instance = I2C1, \ 25 .timing=0x10707DBC, \ 26 .timeout=0x1000, \ 27 .name = "hwi2c1", \ 28 .evirq_type = I2C1_EV_IRQn, \ 29 .erirq_type = I2C1_ER_IRQn, \ 30 } 31 #endif /* I2C1_BUS_CONFIG */ 32 #endif /* BSP_USING_HARD_I2C1 */ 33 34 #ifdef BSP_I2C1_TX_USING_DMA 35 #ifndef I2C1_TX_DMA_CONFIG 36 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 37 #define I2C1_TX_DMA_CONFIG \ 38 { \ 39 .dma_rcc = I2C1_TX_DMA_RCC, \ 40 .Instance = I2C1_TX_DMA_INSTANCE, \ 41 .dma_irq = I2C1_TX_DMA_IRQ, \ 42 .channel = I2C1_TX_DMA_CHANNEL \ 43 } 44 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) 45 #define I2C1_TX_DMA_CONFIG \ 46 { \ 47 .dma_rcc = I2C1_TX_DMA_RCC, \ 48 .Instance = I2C1_TX_DMA_INSTANCE, \ 49 .dma_irq = I2C1_TX_DMA_IRQ, \ 50 .request = DMA_REQUEST_I2C1_TX \ 51 } 52 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ 53 #endif /* I2C1_TX_DMA_CONFIG */ 54 #endif /* BSP_I2C1_TX_USING_DMA */ 55 56 #ifdef BSP_I2C1_RX_USING_DMA 57 #ifndef I2C1_RX_DMA_CONFIG 58 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 59 #define I2C1_RX_DMA_CONFIG \ 60 { \ 61 .dma_rcc = I2C1_RX_DMA_RCC, \ 62 .Instance = I2C1_RX_DMA_INSTANCE, \ 63 .dma_irq = I2C1_RX_DMA_IRQ, \ 64 .channel = I2C1_RX_DMA_CHANNEL, \ 65 } 66 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) 67 #define I2C1_RX_DMA_CONFIG \ 68 { \ 69 .dma_rcc = I2C1_RX_DMA_RCC, \ 70 .Instance = I2C1_RX_DMA_INSTANCE, \ 71 .dma_irq = I2C1_RX_DMA_IRQ, \ 72 .request = DMA_REQUEST_I2C1_RX \ 73 } 74 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ 75 #endif /* I2C1_RX_DMA_CONFIG */ 76 #endif /* BSP_I2C1_RX_USING_DMA */ 77 78 #ifdef BSP_USING_HARD_I2C2 79 #ifndef I2C2_BUS_CONFIG 80 #define I2C2_BUS_CONFIG \ 81 { \ 82 .Instance = I2C2, \ 83 .timing=0x10707DBC, \ 84 .timeout=0x1000, \ 85 .name = "hwi2c2", \ 86 .evirq_type = I2C2_EV_IRQn, \ 87 .erirq_type = I2C2_ER_IRQn, \ 88 } 89 #endif /* I2C2_BUS_CONFIG */ 90 #endif /* BSP_USING_HARD_I2C2 */ 91 92 #ifdef BSP_I2C2_TX_USING_DMA 93 #ifndef I2C2_TX_DMA_CONFIG 94 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 95 #define I2C2_TX_DMA_CONFIG \ 96 { \ 97 .dma_rcc = I2C2_TX_DMA_RCC, \ 98 .Instance = I2C2_TX_DMA_INSTANCE, \ 99 .dma_irq = I2C2_TX_DMA_IRQ, \ 100 .channel = I2C2_TX_DMA_CHANNEL, \ 101 } 102 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) 103 #define I2C2_TX_DMA_CONFIG \ 104 { \ 105 .dma_rcc = I2C2_TX_DMA_RCC, \ 106 .Instance = I2C2_TX_DMA_INSTANCE, \ 107 .dma_irq = I2C2_TX_DMA_IRQ, \ 108 .request = DMA_REQUEST_I2C2_TX \ 109 } 110 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ 111 #endif /* I2C2_TX_DMA_CONFIG */ 112 #endif /* BSP_I2C2_TX_USING_DMA */ 113 114 #ifdef BSP_I2C2_RX_USING_DMA 115 #ifndef I2C2_RX_DMA_CONFIG 116 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 117 #define I2C2_RX_DMA_CONFIG \ 118 { \ 119 .dma_rcc = I2C2_RX_DMA_RCC, \ 120 .Instance = I2C2_RX_DMA_INSTANCE, \ 121 .dma_irq = I2C2_RX_DMA_IRQ, \ 122 .channel = I2C2_RX_DMA_CHANNEL, \ 123 } 124 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) 125 #define I2C2_RX_DMA_CONFIG \ 126 { \ 127 .dma_rcc = I2C2_RX_DMA_RCC, \ 128 .Instance = I2C2_RX_DMA_INSTANCE, \ 129 .dma_irq = I2C2_RX_DMA_IRQ, \ 130 .request = DMA_REQUEST_I2C2_RX \ 131 } 132 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ 133 #endif /* I2C2_RX_DMA_CONFIG */ 134 #endif /* BSP_I2C2_RX_USING_DMA */ 135 136 #ifdef BSP_USING_HARD_I2C3 137 #ifndef I2C3_BUS_CONFIG 138 #define I2C3_BUS_CONFIG \ 139 { \ 140 .Instance = I2C3, \ 141 .timing=0x10707DBC, \ 142 .timeout=0x1000, \ 143 .name = "hwi2c3", \ 144 .evirq_type = I2C3_EV_IRQn, \ 145 .erirq_type = I2C3_ER_IRQn, \ 146 } 147 #endif /* I2C3_BUS_CONFIG */ 148 #endif /* BSP_USING_HARD_I2C3 */ 149 150 #ifdef BSP_I2C3_TX_USING_DMA 151 #ifndef I2C3_TX_DMA_CONFIG 152 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 153 #define I2C3_TX_DMA_CONFIG \ 154 { \ 155 .dma_rcc = I2C3_TX_DMA_RCC, \ 156 .Instance = I2C3_TX_DMA_INSTANCE, \ 157 .dma_irq = I2C3_TX_DMA_IRQ, \ 158 .channel = I2C3_TX_DMA_CHANNEL, \ 159 } 160 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) 161 #define I2C3_TX_DMA_CONFIG \ 162 { \ 163 .dma_rcc = I2C3_TX_DMA_RCC, \ 164 .Instance = I2C3_TX_DMA_INSTANCE, \ 165 .dma_irq = I2C3_TX_DMA_IRQ, \ 166 .request = DMA_REQUEST_I2C3_TX \ 167 } 168 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ 169 #endif /* I2C3_TX_DMA_CONFIG */ 170 #endif /* BSP_I2C3_TX_USING_DMA */ 171 172 #ifdef BSP_I2C3_RX_USING_DMA 173 #ifndef I2C3_RX_DMA_CONFIG 174 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 175 #define I2C3_RX_DMA_CONFIG \ 176 { \ 177 .dma_rcc = I2C3_RX_DMA_RCC, \ 178 .Instance = I2C3_RX_DMA_INSTANCE, \ 179 .dma_irq = I2C3_RX_DMA_IRQ, \ 180 .channel = I2C3_RX_DMA_CHANNEL, \ 181 } 182 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) 183 #define I2C3_RX_DMA_CONFIG \ 184 { \ 185 .dma_rcc = I2C3_RX_DMA_RCC, \ 186 .Instance = I2C3_RX_DMA_INSTANCE, \ 187 .dma_irq = I2C3_RX_DMA_IRQ, \ 188 .request = DMA_REQUEST_I2C3_RX \ 189 } 190 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ 191 #endif /* I2C3_RX_DMA_CONFIG */ 192 #endif /* BSP_I2C3_RX_USING_DMA */ 193 194 #ifdef __cplusplus 195 } 196 #endif 197 198 #endif /*__I2C_CONFIG_H__ */ 199