1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-01-02 zylx first version 9 * 2019-01-08 SummerGift clean up the code 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 stream0 */ 22 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 23 #define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 24 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 25 #define SPI3_RX_DMA_INSTANCE DMA1_Stream0 26 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 27 #define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn 28 #elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) 29 #define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 30 #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 31 #define UART5_RX_DMA_INSTANCE DMA1_Stream0 32 #define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 33 #define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn 34 #endif 35 36 /* DMA1 stream1 */ 37 #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 38 #define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler 39 #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 40 #define UART3_RX_DMA_INSTANCE DMA1_Stream1 41 #define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 42 #define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn 43 #endif 44 45 /* DMA1 stream2 */ 46 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 47 #define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 48 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 49 #define SPI3_RX_DMA_INSTANCE DMA1_Stream2 50 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 51 #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn 52 #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 53 #define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 54 #define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 55 #define UART4_RX_DMA_INSTANCE DMA1_Stream2 56 #define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 57 #define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn 58 #endif 59 60 /* DMA1 stream3 */ 61 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 62 #define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler 63 #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 64 #define SPI2_RX_DMA_INSTANCE DMA1_Stream3 65 #define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 66 #define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn 67 #endif 68 69 /* DMA1 stream4 */ 70 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 71 #define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler 72 #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 73 #define SPI2_TX_DMA_INSTANCE DMA1_Stream4 74 #define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 75 #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn 76 #endif 77 78 79 /* DMA1 stream5 */ 80 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 81 #define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler 82 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 83 #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 84 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 85 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn 86 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 87 #define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler 88 #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 89 #define UART2_RX_DMA_INSTANCE DMA1_Stream5 90 #define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 91 #define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn 92 #endif 93 94 /* DMA1 stream6 */ 95 96 /* DMA1 stream7 */ 97 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 98 #define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler 99 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 100 #define SPI3_TX_DMA_INSTANCE DMA1_Stream7 101 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 102 #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn 103 #endif 104 105 /* DMA2 stream0 */ 106 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 107 #define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler 108 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 109 #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 110 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 111 #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn 112 #elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) 113 #define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler 114 #define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 115 #define SPI4_RX_DMA_INSTANCE DMA2_Stream0 116 #define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 117 #define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn 118 #endif 119 120 /* DMA2 stream1 */ 121 #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 122 #define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler 123 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 124 #define SPI4_TX_DMA_INSTANCE DMA2_Stream1 125 #define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 126 #define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn 127 #endif 128 129 /* DMA2 stream2 */ 130 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 131 #define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 132 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 133 #define SPI1_RX_DMA_INSTANCE DMA2_Stream2 134 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 135 #define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn 136 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 137 #define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 138 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 139 #define UART1_RX_DMA_INSTANCE DMA2_Stream2 140 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 141 #define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn 142 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 143 #define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler 144 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN 145 #define QSPI_DMA_INSTANCE DMA2_Stream2 146 #define QSPI_DMA_CHANNEL DMA_CHANNEL_11 147 #define QSPI_DMA_IRQ DMA2_Stream2_IRQn 148 #endif 149 150 /* DMA2 stream3 */ 151 #if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) 152 #define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler 153 #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 154 #define SPI5_RX_DMA_INSTANCE DMA2_Stream3 155 #define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 156 #define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn 157 #elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 158 #define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler 159 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 160 #define SPI1_TX_DMA_INSTANCE DMA2_Stream3 161 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 162 #define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn 163 #elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) 164 #define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler 165 #define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 166 #define SPI4_RX_DMA_INSTANCE DMA2_Stream3 167 #define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 168 #define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn 169 #endif 170 171 /* DMA2 stream4 */ 172 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 173 #define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler 174 #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 175 #define SPI5_TX_DMA_INSTANCE DMA2_Stream4 176 #define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 177 #define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn 178 #elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 179 #define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler 180 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 181 #define SPI4_TX_DMA_INSTANCE DMA2_Stream4 182 #define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 183 #define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn 184 #endif 185 186 /* DMA2 stream5 */ 187 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 188 #define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler 189 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 190 #define SPI1_TX_DMA_INSTANCE DMA2_Stream5 191 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 192 #define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn 193 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 194 #define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler 195 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 196 #define UART1_RX_DMA_INSTANCE DMA2_Stream5 197 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 198 #define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn 199 #elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) 200 #define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler 201 #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 202 #define SPI5_RX_DMA_INSTANCE DMA2_Stream5 203 #define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 204 #define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn 205 #endif 206 207 /* DMA2 stream6 */ 208 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 209 #define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler 210 #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 211 #define SPI5_TX_DMA_INSTANCE DMA2_Stream6 212 #define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 213 #define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn 214 #endif 215 216 /* DMA2 stream7 */ 217 #if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 218 #define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler 219 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN 220 #define QSPI_DMA_INSTANCE DMA2_Stream7 221 #define QSPI_DMA_CHANNEL DMA_CHANNEL_3 222 #define QSPI_DMA_IRQ DMA2_Stream7_IRQn 223 #endif 224 225 #ifdef __cplusplus 226 } 227 #endif 228 229 #endif /* __DMA_CONFIG_H__ */ 230