1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-01-05 zylx first version 9 * 2019-01-08 SummerGift clean up the code 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #if defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx) 22 #define DMA_Channelx_IRQn DMA1_Ch4_5_DMAMUX1_OVR_IRQn 23 #define DMA_Channelx_IRQHandler DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler 24 #elif defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) 25 #define DMA_Channelx_IRQn DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn 26 #define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler 27 #else 28 #define DMA_Channelx_IRQn DMA1_Ch4_7_DMAMUX1_OVR_IRQn 29 #define DMA_Channelx_IRQHandler DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 30 #endif 31 32 /* DMA1 channel2 */ 33 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 34 #define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler 35 #define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN 36 #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 37 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX 38 #define SPI1_RX_DMA_IRQ DMA1_Channel2_3_IRQn 39 #elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 40 #define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler 41 #define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN 42 #define SPI2_RX_DMA_INSTANCE DMA1_Channel2 43 #define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX 44 #define SPI2_RX_DMA_IRQ DMA1_Channel2_3_IRQn 45 #endif 46 47 /* DMA1 channle3 */ 48 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 49 #define SPI1_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler 50 #define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN 51 #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 52 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX 53 #define SPI1_TX_DMA_IRQ DMA1_Channel2_3_IRQn 54 #elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 55 #define SPI2_DMA_RX_TX_IRQHandler DMA1_Channel2_3_IRQHandler 56 #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN 57 #define SPI2_TX_DMA_INSTANCE DMA1_Channel3 58 #define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX 59 #define SPI2_TX_DMA_IRQ DMA1_Channel2_3_IRQn 60 #endif 61 62 /* DMA1 channle4 */ 63 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 64 #define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler 65 #define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN 66 #define UART1_RX_DMA_INSTANCE DMA1_Channel4 67 #define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX 68 #define UART1_RX_DMA_IRQ DMA_Channelx_IRQn 69 #elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 70 #define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler 71 #define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN 72 #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 73 #define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX 74 #define SPI2_RX_DMA_IRQ DMA_Channelx_IRQn 75 #endif 76 77 /* DMA1 channle5 */ 78 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 79 #define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler 80 #define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN 81 #define UART1_TX_DMA_INSTANCE DMA1_Channel5 82 #define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX 83 #define UART1_TX_DMA_IRQ DMA_Channelx_IRQn 84 #elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 85 #define SPI2_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler 86 #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN 87 #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 88 #define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX 89 #define SPI2_TX_DMA_IRQ DMA_Channelx_IRQn 90 #endif 91 92 #if !(defined(STM32G030xx) || defined(STM32G031xx) || defined(STM32G041xx)) 93 /* DMA1 channle6 */ 94 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 95 #define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler 96 #define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN 97 #define UART2_RX_DMA_INSTANCE DMA1_Channel6 98 #define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX 99 #define UART2_RX_DMA_IRQ DMA_Channelx_IRQn 100 #endif 101 102 /* DMA1 channle7 */ 103 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 104 #define UART_DMA_RX_TX_IRQHandler DMA_Channelx_IRQHandler 105 #define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN 106 #define UART2_TX_DMA_INSTANCE DMA1_Channel7 107 #define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX 108 #define UART2_TX_DMA_IRQ DMA_Channelx_IRQn 109 #endif 110 #endif 111 112 /* DMA1 channle1 */ 113 #if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE) 114 #define LPUART1_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler 115 #define LPUART1_RX_DMA_RCC RCC_AHBENR_DMA1EN 116 #define LPUART1_RX_DMA_INSTANCE DMA1_Channel1 117 #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX 118 #define LPUART1_RX_DMA_IRQ DMA1_Channel1_IRQn 119 #endif 120 121 #ifdef __cplusplus 122 } 123 #endif 124 125 #endif /* __DMA_CONFIG_H__ */ 126