1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-01-02 zylx first version 9 * 2019-01-08 SummerGift clean up the code 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 stream0 */ 22 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 23 #define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 24 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 25 #define SPI3_RX_DMA_INSTANCE DMA1_Stream0 26 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 27 #define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn 28 #elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) 29 #define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 30 #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 31 #define UART5_RX_DMA_INSTANCE DMA1_Stream0 32 #define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4 33 #define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn 34 #elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE) 35 #define UART8_DMA_TX_IRQHandler DMA1_Stream0_IRQHandler 36 #define UART8_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 37 #define UART8_TX_DMA_INSTANCE DMA1_Stream0 38 #define UART8_TX_DMA_CHANNEL DMA_CHANNEL_5 39 #define UART8_TX_DMA_IRQ DMA1_Stream0_IRQn 40 #endif 41 42 /* DMA1 stream1 */ 43 #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 44 #define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler 45 #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 46 #define UART3_RX_DMA_INSTANCE DMA1_Stream1 47 #define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4 48 #define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn 49 #elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) 50 #define UART7_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler 51 #define UART7_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 52 #define UART7_RX_DMA_INSTANCE DMA1_Stream1 53 #define UART7_RX_DMA_CHANNEL DMA_CHANNEL_5 54 #define UART7_RX_DMA_IRQ DMA1_Stream1_IRQn 55 #endif 56 57 /* DMA1 stream2 */ 58 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 59 #define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 60 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 61 #define SPI3_RX_DMA_INSTANCE DMA1_Stream2 62 #define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0 63 #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn 64 #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 65 #define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 66 #define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 67 #define UART4_RX_DMA_INSTANCE DMA1_Stream2 68 #define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4 69 #define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn 70 #endif 71 72 /* DMA1 stream3 */ 73 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 74 #define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler 75 #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 76 #define SPI2_RX_DMA_INSTANCE DMA1_Stream3 77 #define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 78 #define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn 79 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) 80 #define UART3_DMA_TX_IRQHandler DMA1_Stream3_IRQHandler 81 #define UART3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 82 #define UART3_TX_DMA_INSTANCE DMA1_Stream3 83 #define UART3_TX_DMA_CHANNEL DMA_CHANNEL_4 84 #define UART3_TX_DMA_IRQ DMA1_Stream3_IRQn 85 #elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) 86 #define UART7_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler 87 #define UART7_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 88 #define UART7_RX_DMA_INSTANCE DMA1_Stream3 89 #define UART7_RX_DMA_CHANNEL DMA_CHANNEL_5 90 #define UART7_RX_DMA_IRQ DMA1_Stream3_IRQn 91 #endif 92 93 /* DMA1 stream4 */ 94 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 95 #define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler 96 #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 97 #define SPI2_TX_DMA_INSTANCE DMA1_Stream4 98 #define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 99 #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn 100 #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) 101 #define UART4_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler 102 #define UART4_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 103 #define UART4_TX_DMA_INSTANCE DMA1_Stream4 104 #define UART4_TX_DMA_CHANNEL DMA_CHANNEL_4 105 #define UART4_TX_DMA_IRQ DMA1_Stream4_IRQn 106 #endif 107 108 /* DMA1 stream5 */ 109 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 110 #define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler 111 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 112 #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 113 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 114 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn 115 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 116 #define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler 117 #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 118 #define UART2_RX_DMA_INSTANCE DMA1_Stream5 119 #define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 120 #define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn 121 #endif 122 123 /* DMA1 stream6 */ 124 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 125 #define UART2_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler 126 #define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 127 #define UART2_TX_DMA_INSTANCE DMA1_Stream6 128 #define UART2_TX_DMA_CHANNEL DMA_CHANNEL_4 129 #define UART2_TX_DMA_IRQ DMA1_Stream6_IRQn 130 #elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE) 131 #define UART8_DMA_RX_IRQHandler DMA1_Stream6_IRQHandler 132 #define UART8_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 133 #define UART8_RX_DMA_INSTANCE DMA1_Stream6 134 #define UART8_RX_DMA_CHANNEL DMA_CHANNEL_5 135 #define UART8_RX_DMA_IRQ DMA1_Stream6_IRQn 136 #endif 137 138 /* DMA1 stream7 */ 139 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 140 #define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler 141 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 142 #define SPI3_TX_DMA_INSTANCE DMA1_Stream7 143 #define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 144 #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn 145 #elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) 146 #define UART5_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler 147 #define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 148 #define UART5_TX_DMA_INSTANCE DMA1_Stream7 149 #define UART5_TX_DMA_CHANNEL DMA_CHANNEL_4 150 #define UART5_TX_DMA_IRQ DMA1_Stream7_IRQn 151 #endif 152 153 /* DMA2 stream0 */ 154 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 155 #define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler 156 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 157 #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 158 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 159 #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn 160 #elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 161 #define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler 162 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 163 #define SPI4_TX_DMA_INSTANCE DMA2_Stream0 164 #define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 165 #define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn 166 #endif 167 168 /* DMA2 stream1 */ 169 #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 170 #define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler 171 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 172 #define SPI4_TX_DMA_INSTANCE DMA2_Stream1 173 #define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 174 #define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn 175 #elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) 176 #define UART6_DMA_RX_IRQHandler DMA2_Stream1_IRQHandler 177 #define UART6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 178 #define UART6_RX_DMA_INSTANCE DMA2_Stream1 179 #define UART6_RX_DMA_CHANNEL DMA_CHANNEL_5 180 #define UART6_RX_DMA_IRQ DMA2_Stream1_IRQn 181 #endif 182 183 /* DMA2 stream2 */ 184 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 185 #define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 186 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 187 #define SPI1_RX_DMA_INSTANCE DMA2_Stream2 188 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 189 #define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn 190 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 191 #define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 192 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 193 #define UART1_RX_DMA_INSTANCE DMA2_Stream2 194 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 195 #define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn 196 #endif 197 198 /* DMA2 stream3 */ 199 #if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) 200 #define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler 201 #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 202 #define SPI5_RX_DMA_INSTANCE DMA2_Stream3 203 #define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2 204 #define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn 205 #elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 206 #define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler 207 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 208 #define SPI1_TX_DMA_INSTANCE DMA2_Stream3 209 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 210 #define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn 211 #elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 212 #define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler 213 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 214 #define SPI4_TX_DMA_INSTANCE DMA2_Stream3 215 #define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 216 #define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn 217 #endif 218 219 /* DMA2 stream4 */ 220 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 221 #define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler 222 #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 223 #define SPI5_TX_DMA_INSTANCE DMA2_Stream4 224 #define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 225 #define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn 226 #elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 227 #define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler 228 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 229 #define SPI4_TX_DMA_INSTANCE DMA2_Stream4 230 #define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 231 #define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn 232 #endif 233 234 /* DMA2 stream5 */ 235 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 236 #define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler 237 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 238 #define SPI1_TX_DMA_INSTANCE DMA2_Stream5 239 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 240 #define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn 241 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 242 #define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler 243 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 244 #define UART1_RX_DMA_INSTANCE DMA2_Stream5 245 #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4 246 #define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn 247 #elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) 248 #define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler 249 #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 250 #define SPI5_RX_DMA_INSTANCE DMA2_Stream5 251 #define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 252 #define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn 253 #endif 254 255 /* DMA2 stream6 */ 256 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 257 #define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler 258 #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 259 #define SPI5_TX_DMA_INSTANCE DMA2_Stream6 260 #define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 261 #define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn 262 #elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) 263 #define UART6_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler 264 #define UART6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 265 #define UART6_TX_DMA_INSTANCE DMA2_Stream6 266 #define UART6_TX_DMA_CHANNEL DMA_CHANNEL_5 267 #define UART6_TX_DMA_IRQ DMA2_Stream6_IRQn 268 #endif 269 270 /* DMA2 stream7 */ 271 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 272 #define UART1_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler 273 #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 274 #define UART1_TX_DMA_INSTANCE DMA2_Stream7 275 #define UART1_TX_DMA_CHANNEL DMA_CHANNEL_4 276 #define UART1_TX_DMA_IRQ DMA2_Stream7_IRQn 277 #endif 278 279 #ifdef __cplusplus 280 } 281 #endif 282 283 284 #endif /* __DMA_CONFIG_H__ */ 285