1 /*
2  * Copyright (c) 2006-2023, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-12-22     zylx         first version
9  */
10 
11 #ifndef __QSPI_CONFIG_H__
12 #define __QSPI_CONFIG_H__
13 
14 #include <rtthread.h>
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 #ifdef BSP_USING_QSPI
21 #ifndef QSPI_BUS_CONFIG
22 #define QSPI_BUS_CONFIG                                        \
23     {                                                          \
24         .Instance = QUADSPI,                                   \
25         .Init.FifoThreshold = 4,                               \
26         .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
27         .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE,  \
28     }
29 #endif /* QSPI_BUS_CONFIG */
30 #endif /* BSP_USING_QSPI */
31 
32 #ifdef BSP_QSPI_USING_DMA
33 #ifndef QSPI_DMA_CONFIG
34 #define QSPI_DMA_CONFIG                                        \
35     {                                                          \
36         .Instance = QSPI_DMA_INSTANCE,                         \
37         .Init.Channel  = QSPI_DMA_CHANNEL,                     \
38         .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
39         .Init.PeriphInc = DMA_PINC_DISABLE,                    \
40         .Init.MemInc = DMA_MINC_ENABLE,                        \
41         .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
42         .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
43         .Init.Mode = DMA_NORMAL,                               \
44         .Init.Priority = DMA_PRIORITY_LOW                      \
45     }
46 #endif /* QSPI_DMA_CONFIG */
47 #endif /* BSP_QSPI_USING_DMA */
48 
49 #define QSPI_IRQn                   QUADSPI_IRQn
50 #define QSPI_IRQHandler             QUADSPI_IRQHandler
51 
52 #ifdef __cplusplus
53 }
54 #endif
55 
56 #endif /* __QSPI_CONFIG_H__ */
57