1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-01-02 zylx first version 9 * 2019-01-08 SummerGift clean up the code 10 * 2020-05-02 whj4674672 support stm32h7 dma1 and dma2 11 */ 12 13 #ifndef __DMA_CONFIG_H__ 14 #define __DMA_CONFIG_H__ 15 16 #include <rtthread.h> 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /* DMA1 stream0 */ 23 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 24 #define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler 25 #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 26 #define UART2_RX_DMA_INSTANCE DMA1_Stream0 27 #define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX 28 #define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn 29 #endif 30 31 /* DMA1 stream1 */ 32 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 33 #define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler 34 #define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 35 #define UART2_TX_DMA_INSTANCE DMA1_Stream1 36 #define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX 37 #define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn 38 #endif 39 40 /* DMA1 stream2 */ 41 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 42 #define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler 43 #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 44 #define SPI3_RX_DMA_INSTANCE DMA1_Stream2 45 #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn 46 #endif 47 48 /* DMA1 stream3 */ 49 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 50 #define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler 51 #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 52 #define SPI2_RX_DMA_INSTANCE DMA1_Stream3 53 #define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn 54 #endif 55 56 /* DMA1 stream4 */ 57 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 58 #define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler 59 #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 60 #define SPI2_TX_DMA_INSTANCE DMA1_Stream4 61 #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn 62 #endif 63 64 65 /* DMA1 stream5 */ 66 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 67 #define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler 68 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 69 #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 70 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn 71 #endif 72 73 /* DMA1 stream6 */ 74 75 /* DMA1 stream7 */ 76 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 77 #define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler 78 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 79 #define SPI3_TX_DMA_INSTANCE DMA1_Stream7 80 #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn 81 #endif 82 83 /* DMA2 stream0 */ 84 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 85 #define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler 86 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 87 #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 88 #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn 89 #endif 90 91 /* DMA2 stream1 */ 92 #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 93 #define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler 94 #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 95 #define SPI4_TX_DMA_INSTANCE DMA2_Stream1 96 #define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn 97 #endif 98 99 /* DMA2 stream2 */ 100 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 101 #define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler 102 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 103 #define SPI1_RX_DMA_INSTANCE DMA2_Stream2 104 #define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn 105 #endif 106 107 /* DMA2 stream3 */ 108 #if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) 109 #define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler 110 #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 111 #define SPI5_RX_DMA_INSTANCE DMA2_Stream3 112 #define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn 113 #endif 114 115 /* DMA2 stream4 */ 116 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 117 #define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler 118 #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 119 #define SPI5_TX_DMA_INSTANCE DMA2_Stream4 120 #define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn 121 #endif 122 123 /* DMA2 stream5 */ 124 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 125 #define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler 126 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 127 #define SPI1_TX_DMA_INSTANCE DMA2_Stream5 128 #define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn 129 #endif 130 131 /* DMA2 stream6 */ 132 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 133 #define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler 134 #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 135 #define SPI5_TX_DMA_INSTANCE DMA2_Stream6 136 #define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn 137 #endif 138 139 /* DMA2 stream7 */ 140 #if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 141 #define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler 142 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN 143 #define QSPI_DMA_INSTANCE DMA2_Stream7 144 #define QSPI_DMA_IRQ DMA2_Stream7_IRQn 145 #endif 146 147 #ifdef __cplusplus 148 } 149 #endif 150 151 #endif /* __DMA_CONFIG_H__ */ 152