1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-01-02 SummerGift first version 9 * 2019-01-08 SummerGift clean up the code 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 channel1 */ 22 /* DMA1 channel2 */ 23 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 24 #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler 25 #define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN 26 #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 27 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn 28 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) 29 #define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler 30 #define UART3_TX_DMA_RCC RCC_AHBENR_DMA1EN 31 #define UART3_TX_DMA_INSTANCE DMA1_Channel2 32 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn 33 #endif 34 35 /* DMA1 channel3 */ 36 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 37 #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler 38 #define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN 39 #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 40 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn 41 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 42 #define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler 43 #define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN 44 #define UART3_RX_DMA_INSTANCE DMA1_Channel3 45 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn 46 #endif 47 48 /* DMA1 channel4 */ 49 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 50 #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler 51 #define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN 52 #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 53 #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn 54 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 55 #define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler 56 #define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN 57 #define UART1_TX_DMA_INSTANCE DMA1_Channel4 58 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn 59 #endif 60 61 /* DMA1 channel5 */ 62 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 63 #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler 64 #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN 65 #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 66 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn 67 68 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 69 #define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler 70 #define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN 71 #define UART1_RX_DMA_INSTANCE DMA1_Channel5 72 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn 73 #endif 74 75 /* DMA1 channel6 */ 76 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 77 #define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler 78 #define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN 79 #define UART2_RX_DMA_INSTANCE DMA1_Channel6 80 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn 81 #endif 82 83 /* DMA1 channel7 */ 84 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 85 #define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler 86 #define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN 87 #define UART2_TX_DMA_INSTANCE DMA1_Channel7 88 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn 89 #endif 90 91 /* DMA2 channel1 */ 92 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 93 #define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler 94 #define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN 95 #define SPI3_RX_DMA_INSTANCE DMA2_Channel1 96 #define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn 97 #endif 98 99 /* DMA2 channel2 */ 100 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 101 #define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler 102 #define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN 103 #define SPI3_TX_DMA_INSTANCE DMA2_Channel2 104 #define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn 105 #endif 106 107 /* DMA2 channel3 */ 108 #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 109 #define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler 110 #define UART4_RX_DMA_RCC RCC_AHBENR_DMA2EN 111 #define UART4_RX_DMA_INSTANCE DMA2_Channel3 112 #define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn 113 #endif 114 /* DMA2 channel4 */ 115 /* DMA2 channel5 */ 116 #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) 117 #define UART4_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler 118 #define UART4_TX_DMA_RCC RCC_AHBENR_DMA2EN 119 #define UART4_TX_DMA_INSTANCE DMA2_Channel5 120 #define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn 121 #endif 122 123 #ifdef __cplusplus 124 } 125 #endif 126 127 #endif /* __DMA_CONFIG_H__ */ 128