1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-01-05 zylx first version 9 * 2019-01-08 SummerGift clean up the code 10 * 2019-12-01 armink add DMAMUX support 11 */ 12 13 #ifndef __DMA_CONFIG_H__ 14 #define __DMA_CONFIG_H__ 15 16 #include <rtthread.h> 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /* DMA1 channel1 */ 23 24 /* DMA1 channel2 */ 25 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 26 #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler 27 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 28 #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 29 #if defined(DMAMUX1) /* for L4+ */ 30 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX 31 #else /* for L4 */ 32 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_1 33 #endif /* DMAMUX1 */ 34 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn 35 #endif 36 37 /* DMA1 channel3 */ 38 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 39 #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler 40 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 41 #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 42 #if defined(DMAMUX1) /* for L4+ */ 43 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX 44 #else /* for L4 */ 45 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_1 46 #endif /* DMAMUX1 */ 47 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn 48 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 49 #define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler 50 #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 51 #define UART3_RX_DMA_INSTANCE DMA1_Channel3 52 #if defined(DMAMUX1) /* for L4+ */ 53 #define UART3_RX_DMA_REQUEST DMA_REQUEST_USART3_RX 54 #else /* for L4 */ 55 #define UART3_RX_DMA_REQUEST DMA_REQUEST_2 56 #endif /* DMAMUX1 */ 57 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn 58 #endif 59 60 /* DMA1 channel4 */ 61 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 62 #define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler 63 #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 64 #define UART1_TX_DMA_INSTANCE DMA1_Channel4 65 #if defined(DMAMUX1) /* for L4+ */ 66 #define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX 67 #else /* for L4 */ 68 #define UART1_TX_DMA_REQUEST DMA_REQUEST_2 69 #endif /* DMAMUX1 */ 70 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn 71 #elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 72 #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler 73 #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 74 #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 75 #if defined(DMAMUX1) /* for L4+ */ 76 #define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX 77 #else /* for L4 */ 78 #define SPI2_RX_DMA_REQUEST DMA_REQUEST_1 79 #endif /* DMAMUX1 */ 80 #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn 81 #endif 82 83 /* DMA1 channel5 */ 84 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 85 #define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler 86 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 87 #define UART1_RX_DMA_INSTANCE DMA1_Channel5 88 #if defined(DMAMUX1) /* for L4+ */ 89 #define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX 90 #else /* for L4 */ 91 #define UART1_RX_DMA_REQUEST DMA_REQUEST_2 92 #endif /* DMAMUX1 */ 93 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn 94 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 95 #define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler 96 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN 97 #define QSPI_DMA_INSTANCE DMA1_Channel5 98 #if defined(DMAMUX1) /* for L4+ */ 99 #define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1 100 #else /* for L4 */ 101 #define QSPI_DMA_REQUEST DMA_REQUEST_5 102 #endif /* DMAMUX1 */ 103 #define QSPI_DMA_IRQ DMA1_Channel5_IRQn 104 #elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 105 #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler 106 #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 107 #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 108 #if defined(DMAMUX1) /* for L4+ */ 109 #define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX 110 #else /* for L4 */ 111 #define SPI2_TX_DMA_REQUEST DMA_REQUEST_1 112 #endif /* DMAMUX1 */ 113 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn 114 #endif 115 116 /* DMA1 channel6 */ 117 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 118 #define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler 119 #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 120 #define UART2_RX_DMA_INSTANCE DMA1_Channel6 121 #if defined(DMAMUX1) /* for L4+ */ 122 #define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX 123 #else /* for L4 */ 124 #define UART2_RX_DMA_REQUEST DMA_REQUEST_2 125 #endif /* DMAMUX1 */ 126 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn 127 #endif 128 129 /* DMA1 channel7 */ 130 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 131 #define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler 132 #define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 133 #define UART2_TX_DMA_INSTANCE DMA1_Channel7 134 #if defined(DMAMUX1) /* for L4+ */ 135 #define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX 136 #else /* for L4 */ 137 #define UART2_TX_DMA_REQUEST DMA_REQUEST_2 138 #endif /* DMAMUX1 */ 139 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn 140 #endif 141 142 /* DMA2 channel1 */ 143 #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) 144 #define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler 145 #define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 146 #define UART5_TX_DMA_INSTANCE DMA2_Channel1 147 #if defined(DMAMUX1) /* for L4+ */ 148 #define UART5_TX_DMA_REQUEST DMA_REQUEST_UART5_TX 149 #else /* for L4 */ 150 #define UART5_TX_DMA_REQUEST DMA_REQUEST_2 151 #endif /* DMAMUX1 */ 152 #define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn 153 #endif 154 155 /* DMA2 channel2 */ 156 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 157 #define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler 158 #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 159 #define SPI3_TX_DMA_INSTANCE DMA2_Channel2 160 #if defined(DMAMUX1) /* for L4+ */ 161 #define SPI3_TX_DMA_REQUEST DMA_REQUEST_SPI3_TX 162 #else /* for L4 */ 163 #define SPI3_TX_DMA_REQUEST DMA_REQUEST_3 164 #endif /* DMAMUX1 */ 165 #define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn 166 #elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) 167 #define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler 168 #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 169 #define UART5_RX_DMA_INSTANCE DMA2_Channel2 170 #if defined(DMAMUX1) /* for L4+ */ 171 #define UART5_RX_DMA_REQUEST DMA_REQUEST_UART5_RX 172 #else /* for L4 */ 173 #define UART5_RX_DMA_REQUEST DMA_REQUEST_2 174 #endif /* DMAMUX1 */ 175 #define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn 176 #endif 177 178 /* DMA2 channel3 */ 179 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 180 #define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler 181 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 182 #define SPI1_RX_DMA_INSTANCE DMA2_Channel3 183 #if defined(DMAMUX1) /* for L4+ */ 184 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX 185 #else /* for L4 */ 186 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_4 187 #endif /* DMAMUX1 */ 188 #define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn 189 #endif 190 191 /* DMA2 channel4 */ 192 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 193 #define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler 194 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 195 #define SPI1_TX_DMA_INSTANCE DMA2_Channel4 196 #if defined(DMAMUX1) /* for L4+ */ 197 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX 198 #else /* for L4 */ 199 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_4 200 #endif /* DMAMUX1 */ 201 #define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn 202 #endif 203 204 /* DMA2 channel5 */ 205 206 /* DMA2 channel6 */ 207 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 208 #define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler 209 #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 210 #define UART1_TX_DMA_INSTANCE DMA2_Channel6 211 #if defined(DMAMUX1) /* for L4+ */ 212 #define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX 213 #else /* for L4 */ 214 #define UART1_TX_DMA_REQUEST DMA_REQUEST_2 215 #endif /* DMAMUX1 */ 216 #define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn 217 #endif 218 219 /* DMA2 channel7 */ 220 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 221 #define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler 222 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 223 #define UART1_RX_DMA_INSTANCE DMA2_Channel7 224 #if defined(DMAMUX1) /* for L4+ */ 225 #define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX 226 #else /* for L4 */ 227 #define UART1_RX_DMA_REQUEST DMA_REQUEST_2 228 #endif /* DMAMUX1 */ 229 #define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn 230 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 231 #define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler 232 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN 233 #define QSPI_DMA_INSTANCE DMA2_Channel7 234 #if defined(DMAMUX1) /* for L4+ */ 235 #define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1 236 #else /* for L4 */ 237 #define QSPI_DMA_REQUEST DMA_REQUEST_3 238 #endif /* DMAMUX1 */ 239 #define QSPI_DMA_IRQ DMA2_Channel7_IRQn 240 #elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE) 241 #define LPUART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler 242 #define LPUART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 243 #define LPUART1_RX_DMA_INSTANCE DMA2_Channel7 244 #if defined(DMAMUX1) /* for L4+ */ 245 #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX 246 #else /* for L4 */ 247 #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_4 248 #endif /* DMAMUX1 */ 249 #define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn 250 #endif 251 252 #ifdef __cplusplus 253 } 254 #endif 255 256 #endif /* __DMA_CONFIG_H__ */ 257