1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * Date Author Notes 9 * 2020-10-14 Dozingfiretruck first version 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 channel1 */ 22 23 /* DMA1 channel2 */ 24 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 25 #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler 26 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 27 #define SPI1_RX_DMA_INSTANCE DMA1_Channel2 28 #if defined(DMAMUX1) /* for L4+ */ 29 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX 30 #else /* for L4 */ 31 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_1 32 #endif /* DMAMUX1 */ 33 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn 34 #endif 35 36 /* DMA1 channel3 */ 37 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 38 #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler 39 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 40 #define SPI1_TX_DMA_INSTANCE DMA1_Channel3 41 #if defined(DMAMUX1) /* for L4+ */ 42 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX 43 #else /* for L4 */ 44 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_1 45 #endif /* DMAMUX1 */ 46 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn 47 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 48 #define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler 49 #define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 50 #define UART3_RX_DMA_INSTANCE DMA1_Channel3 51 #if defined(DMAMUX1) /* for L4+ */ 52 #define UART3_RX_DMA_REQUEST DMA_REQUEST_USART3_RX 53 #else /* for L4 */ 54 #define UART3_RX_DMA_REQUEST DMA_REQUEST_2 55 #endif /* DMAMUX1 */ 56 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn 57 #endif 58 59 /* DMA1 channel4 */ 60 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 61 #define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler 62 #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 63 #define UART1_TX_DMA_INSTANCE DMA1_Channel4 64 #if defined(DMAMUX1) /* for L4+ */ 65 #define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX 66 #else /* for L4 */ 67 #define UART1_TX_DMA_REQUEST DMA_REQUEST_2 68 #endif /* DMAMUX1 */ 69 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn 70 #elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 71 #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler 72 #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 73 #define SPI2_RX_DMA_INSTANCE DMA1_Channel4 74 #if defined(DMAMUX1) /* for L4+ */ 75 #define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX 76 #else /* for L4 */ 77 #define SPI2_RX_DMA_REQUEST DMA_REQUEST_1 78 #endif /* DMAMUX1 */ 79 #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn 80 #endif 81 82 /* DMA1 channel5 */ 83 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 84 #define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler 85 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 86 #define UART1_RX_DMA_INSTANCE DMA1_Channel5 87 #if defined(DMAMUX1) /* for L4+ */ 88 #define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX 89 #else /* for L4 */ 90 #define UART1_RX_DMA_REQUEST DMA_REQUEST_2 91 #endif /* DMAMUX1 */ 92 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn 93 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 94 #define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler 95 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN 96 #define QSPI_DMA_INSTANCE DMA1_Channel5 97 #if defined(DMAMUX1) /* for L4+ */ 98 #define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1 99 #else /* for L4 */ 100 #define QSPI_DMA_REQUEST DMA_REQUEST_5 101 #endif /* DMAMUX1 */ 102 #define QSPI_DMA_IRQ DMA1_Channel5_IRQn 103 #elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 104 #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler 105 #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN 106 #define SPI2_TX_DMA_INSTANCE DMA1_Channel5 107 #if defined(DMAMUX1) /* for L4+ */ 108 #define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX 109 #else /* for L4 */ 110 #define SPI2_TX_DMA_REQUEST DMA_REQUEST_1 111 #endif /* DMAMUX1 */ 112 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn 113 #endif 114 115 /* DMA1 channel6 */ 116 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 117 #define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler 118 #define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN 119 #define UART2_RX_DMA_INSTANCE DMA1_Channel6 120 #if defined(DMAMUX1) /* for L4+ */ 121 #define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX 122 #else /* for L4 */ 123 #define UART2_RX_DMA_REQUEST DMA_REQUEST_2 124 #endif /* DMAMUX1 */ 125 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn 126 #endif 127 128 /* DMA1 channel7 */ 129 130 /* DMA2 channel1 */ 131 #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) 132 #define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler 133 #define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 134 #define UART5_TX_DMA_INSTANCE DMA2_Channel1 135 #if defined(DMAMUX1) /* for L4+ */ 136 #define UART5_TX_DMA_REQUEST DMA_REQUEST_UART5_TX 137 #else /* for L4 */ 138 #define UART5_TX_DMA_REQUEST DMA_REQUEST_2 139 #endif /* DMAMUX1 */ 140 #define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn 141 #endif 142 143 /* DMA2 channel2 */ 144 #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) 145 #define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler 146 #define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 147 #define UART5_RX_DMA_INSTANCE DMA2_Channel2 148 #if defined(DMAMUX1) /* for L4+ */ 149 #define UART5_RX_DMA_REQUEST DMA_REQUEST_UART5_RX 150 #else /* for L4 */ 151 #define UART5_RX_DMA_REQUEST DMA_REQUEST_2 152 #endif /* DMAMUX1 */ 153 #define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn 154 #endif 155 156 /* DMA2 channel3 */ 157 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 158 #define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler 159 #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 160 #define SPI1_RX_DMA_INSTANCE DMA2_Channel3 161 #if defined(DMAMUX1) /* for L4+ */ 162 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX 163 #else /* for L4 */ 164 #define SPI1_RX_DMA_REQUEST DMA_REQUEST_4 165 #endif /* DMAMUX1 */ 166 #define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn 167 #endif 168 169 /* DMA2 channel4 */ 170 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 171 #define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler 172 #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 173 #define SPI1_TX_DMA_INSTANCE DMA2_Channel4 174 #if defined(DMAMUX1) /* for L4+ */ 175 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX 176 #else /* for L4 */ 177 #define SPI1_TX_DMA_REQUEST DMA_REQUEST_4 178 #endif /* DMAMUX1 */ 179 #define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn 180 #endif 181 182 /* DMA2 channel5 */ 183 184 /* DMA2 channel6 */ 185 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 186 #define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler 187 #define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN 188 #define UART1_TX_DMA_INSTANCE DMA2_Channel6 189 #if defined(DMAMUX1) /* for L4+ */ 190 #define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX 191 #else /* for L4 */ 192 #define UART1_TX_DMA_REQUEST DMA_REQUEST_2 193 #endif /* DMAMUX1 */ 194 #define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn 195 #endif 196 197 /* DMA2 channel7 */ 198 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 199 #define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler 200 #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 201 #define UART1_RX_DMA_INSTANCE DMA2_Channel7 202 #if defined(DMAMUX1) /* for L4+ */ 203 #define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX 204 #else /* for L4 */ 205 #define UART1_RX_DMA_REQUEST DMA_REQUEST_2 206 #endif /* DMAMUX1 */ 207 #define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn 208 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 209 #define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler 210 #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN 211 #define QSPI_DMA_INSTANCE DMA2_Channel7 212 #if defined(DMAMUX1) /* for L4+ */ 213 #define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1 214 #else /* for L4 */ 215 #define QSPI_DMA_REQUEST DMA_REQUEST_3 216 #endif /* DMAMUX1 */ 217 #define QSPI_DMA_IRQ DMA2_Channel7_IRQn 218 #elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE) 219 #define LPUART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler 220 #define LPUART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN 221 #define LPUART1_RX_DMA_INSTANCE DMA2_Channel7 222 #if defined(DMAMUX1) /* for L4+ */ 223 #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX 224 #else /* for L4 */ 225 #define LPUART1_RX_DMA_REQUEST DMA_REQUEST_4 226 #endif /* DMAMUX1 */ 227 #define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn 228 #endif 229 230 #ifdef __cplusplus 231 } 232 #endif 233 234 #endif /* __DMA_CONFIG_H__ */ 235