1 /*
2 * Copyright (c) 2006-2024, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-10-30 SummerGift first version
9 * 2020-03-16 SummerGift add device close feature
10 * 2020-03-20 SummerGift fix bug caused by ORE
11 * 2020-05-02 whj4674672 support stm32h7 uart dma
12 * 2020-09-09 forest-rain support stm32wl uart
13 * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
14 */
15
16 #include "board.h"
17 #include "drv_usart.h"
18 #include "drv_config.h"
19
20 #ifdef RT_USING_SERIAL
21
22 //#define DRV_DEBUG
23 #define LOG_TAG "drv.usart"
24 #include <drv_log.h>
25
26 #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
27 !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
28 !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
29 #error "Please define at least one BSP_USING_UARTx"
30 /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
31 #endif
32
33 #ifdef RT_SERIAL_USING_DMA
34 static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
35 #endif
36
37 enum
38 {
39 #ifdef BSP_USING_UART1
40 UART1_INDEX,
41 #endif
42 #ifdef BSP_USING_UART2
43 UART2_INDEX,
44 #endif
45 #ifdef BSP_USING_UART3
46 UART3_INDEX,
47 #endif
48 #ifdef BSP_USING_UART4
49 UART4_INDEX,
50 #endif
51 #ifdef BSP_USING_UART5
52 UART5_INDEX,
53 #endif
54 #ifdef BSP_USING_UART6
55 UART6_INDEX,
56 #endif
57 #ifdef BSP_USING_UART7
58 UART7_INDEX,
59 #endif
60 #ifdef BSP_USING_UART8
61 UART8_INDEX,
62 #endif
63 #ifdef BSP_USING_LPUART1
64 LPUART1_INDEX,
65 #endif
66 };
67
68 static struct stm32_uart_config uart_config[] =
69 {
70 #ifdef BSP_USING_UART1
71 UART1_CONFIG,
72 #endif
73 #ifdef BSP_USING_UART2
74 UART2_CONFIG,
75 #endif
76 #ifdef BSP_USING_UART3
77 UART3_CONFIG,
78 #endif
79 #ifdef BSP_USING_UART4
80 UART4_CONFIG,
81 #endif
82 #ifdef BSP_USING_UART5
83 UART5_CONFIG,
84 #endif
85 #ifdef BSP_USING_UART6
86 UART6_CONFIG,
87 #endif
88 #ifdef BSP_USING_UART7
89 UART7_CONFIG,
90 #endif
91 #ifdef BSP_USING_UART8
92 UART8_CONFIG,
93 #endif
94 #ifdef BSP_USING_LPUART1
95 LPUART1_CONFIG,
96 #endif
97 };
98
99 static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
100
stm32_uart_get_mask(rt_uint32_t word_length,rt_uint32_t parity)101 rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
102 {
103 rt_uint32_t mask = 0x00FFU;
104 if (word_length == UART_WORDLENGTH_8B)
105 {
106 if (parity == UART_PARITY_NONE)
107 {
108 mask = 0x00FFU ;
109 }
110 else
111 {
112 mask = 0x007FU ;
113 }
114 }
115 #ifdef UART_WORDLENGTH_9B
116 else if (word_length == UART_WORDLENGTH_9B)
117 {
118 if (parity == UART_PARITY_NONE)
119 {
120 mask = 0x01FFU ;
121 }
122 else
123 {
124 mask = 0x00FFU ;
125 }
126 }
127 #endif
128 #ifdef UART_WORDLENGTH_7B
129 else if (word_length == UART_WORDLENGTH_7B)
130 {
131 if (parity == UART_PARITY_NONE)
132 {
133 mask = 0x007FU ;
134 }
135 else
136 {
137 mask = 0x003FU ;
138 }
139 }
140 else
141 {
142 mask = 0x0000U;
143 }
144 #endif
145 return mask;
146 }
147
stm32_configure(struct rt_serial_device * serial,struct serial_configure * cfg)148 static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
149 {
150 struct stm32_uart *uart;
151 RT_ASSERT(serial != RT_NULL);
152 RT_ASSERT(cfg != RT_NULL);
153
154 uart = rt_container_of(serial, struct stm32_uart, serial);
155 uart->handle.Instance = uart->config->Instance;
156 uart->handle.Init.BaudRate = cfg->baud_rate;
157 uart->handle.Init.Mode = UART_MODE_TX_RX;
158 #ifdef USART_CR1_OVER8
159 uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16;
160 #else
161 uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
162 #endif /* USART_CR1_OVER8 */
163
164 switch (cfg->flowcontrol)
165 {
166 case RT_SERIAL_FLOWCONTROL_NONE:
167 uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
168 break;
169 case RT_SERIAL_FLOWCONTROL_CTSRTS:
170 uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
171 break;
172 default:
173 uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
174 break;
175 }
176
177 switch (cfg->data_bits)
178 {
179 case DATA_BITS_8:
180 if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
181 uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
182 else
183 uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
184 break;
185 case DATA_BITS_9:
186 uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
187 break;
188 default:
189 uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
190 break;
191 }
192
193 switch (cfg->stop_bits)
194 {
195 case STOP_BITS_1:
196 uart->handle.Init.StopBits = UART_STOPBITS_1;
197 break;
198 case STOP_BITS_2:
199 uart->handle.Init.StopBits = UART_STOPBITS_2;
200 break;
201 default:
202 uart->handle.Init.StopBits = UART_STOPBITS_1;
203 break;
204 }
205
206 switch (cfg->parity)
207 {
208 case PARITY_NONE:
209 uart->handle.Init.Parity = UART_PARITY_NONE;
210 break;
211 case PARITY_ODD:
212 uart->handle.Init.Parity = UART_PARITY_ODD;
213 break;
214 case PARITY_EVEN:
215 uart->handle.Init.Parity = UART_PARITY_EVEN;
216 break;
217 default:
218 uart->handle.Init.Parity = UART_PARITY_NONE;
219 break;
220 }
221
222 #ifdef RT_SERIAL_USING_DMA
223 if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
224 uart->dma_rx.remaining_cnt = cfg->bufsz;
225 }
226 #endif
227
228 if (HAL_UART_Init(&uart->handle) != HAL_OK)
229 {
230 return -RT_ERROR;
231 }
232 uart->DR_mask = stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
233 uart->tx_block_timeout = BSP_STM32_UART_V1_TX_TIMEOUT;
234 return RT_EOK;
235 }
236
stm32_control(struct rt_serial_device * serial,int cmd,void * arg)237 static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
238 {
239 struct stm32_uart *uart;
240 #ifdef RT_SERIAL_USING_DMA
241 rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
242 #endif
243
244 RT_ASSERT(serial != RT_NULL);
245 uart = rt_container_of(serial, struct stm32_uart, serial);
246
247 switch (cmd)
248 {
249 /* disable interrupt */
250 case RT_DEVICE_CTRL_CLR_INT:
251 {
252 /* disable uart irq */
253 NVIC_DisableIRQ(uart->config->irq_type);
254 rt_uint32_t direction = (rt_uint32_t)arg;
255 if(direction == RT_DEVICE_FLAG_INT_RX)
256 {
257 /* disable interrupt */
258 __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
259 }
260
261 #ifdef RT_SERIAL_USING_DMA
262 /* disable DMA */
263 if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
264 {
265 HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
266 if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
267 {
268 RT_ASSERT(0);
269 }
270
271 if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
272 {
273 RT_ASSERT(0);
274 }
275 }
276 else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
277 {
278 HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
279 if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
280 {
281 RT_ASSERT(0);
282 }
283 }
284 #endif
285 break;
286 }
287
288 /* enable interrupt */
289 case RT_DEVICE_CTRL_SET_INT:
290 {
291 /* enable uart irq */
292 HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
293 HAL_NVIC_EnableIRQ(uart->config->irq_type);
294 rt_uint32_t direction = (rt_uint32_t)arg;
295 if(direction == RT_DEVICE_FLAG_INT_RX)
296 {
297 /* enable interrupt */
298 __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
299 }
300 break;
301 }
302
303 #ifdef RT_SERIAL_USING_DMA
304 case RT_DEVICE_CTRL_CONFIG:
305 {
306 stm32_dma_config(serial, ctrl_arg);
307 break;
308 }
309 #endif
310
311 case RT_DEVICE_CTRL_CLOSE:
312 {
313 if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
314 {
315 RT_ASSERT(0)
316 }
317 break;
318 }
319
320 case UART_CTRL_SET_BLOCK_TIMEOUT:
321 {
322 rt_uint32_t block_timeout = (rt_uint32_t)arg;
323 if(block_timeout > 0)
324 {
325 uart->tx_block_timeout = block_timeout;
326 }
327 else
328 {
329 return -RT_ERROR;
330 }
331 break;
332 }
333
334 default:
335 break;
336 }
337 return RT_EOK;
338 }
339
stm32_putc(struct rt_serial_device * serial,char c)340 static int stm32_putc(struct rt_serial_device *serial, char c)
341 {
342 struct stm32_uart *uart;
343 RT_ASSERT(serial != RT_NULL);
344
345 uart = rt_container_of(serial, struct stm32_uart, serial);
346 rt_uint32_t block_timeout = uart->tx_block_timeout;
347 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
348 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
349 || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
350 || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \
351 || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
352 uart->handle.Instance->TDR = c;
353 #else
354 uart->handle.Instance->DR = c;
355 #endif
356 while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET && --block_timeout);
357 return (block_timeout != 0) ? 1 : -1;
358 }
359
stm32_getc(struct rt_serial_device * serial)360 static int stm32_getc(struct rt_serial_device *serial)
361 {
362 int ch;
363 struct stm32_uart *uart;
364 RT_ASSERT(serial != RT_NULL);
365 uart = rt_container_of(serial, struct stm32_uart, serial);
366
367 ch = -1;
368 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
369 {
370 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
371 || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
372 || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
373 || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
374 ch = uart->handle.Instance->RDR & uart->DR_mask;
375 #else
376 ch = uart->handle.Instance->DR & uart->DR_mask;
377 #endif
378 }
379 return ch;
380 }
381
stm32_dma_transmit(struct rt_serial_device * serial,rt_uint8_t * buf,rt_size_t size,int direction)382 static rt_ssize_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
383 {
384 struct stm32_uart *uart;
385 RT_ASSERT(serial != RT_NULL);
386 RT_ASSERT(buf != RT_NULL);
387 uart = rt_container_of(serial, struct stm32_uart, serial);
388
389 if (size == 0)
390 {
391 return 0;
392 }
393
394 if (RT_SERIAL_DMA_TX == direction)
395 {
396 if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
397 {
398 return size;
399 }
400 else
401 {
402 return 0;
403 }
404 }
405 return 0;
406 }
407
408 #ifdef RT_SERIAL_USING_DMA
dma_recv_isr(struct rt_serial_device * serial,rt_uint8_t isr_flag)409 static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
410 {
411 struct stm32_uart *uart;
412 rt_base_t level;
413 rt_size_t recv_len, counter;
414
415 RT_ASSERT(serial != RT_NULL);
416 uart = rt_container_of(serial, struct stm32_uart, serial);
417
418 level = rt_hw_interrupt_disable();
419 recv_len = 0;
420 counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
421
422 switch (isr_flag)
423 {
424 case UART_RX_DMA_IT_IDLE_FLAG:
425 if (counter <= uart->dma_rx.remaining_cnt)
426 recv_len = uart->dma_rx.remaining_cnt - counter;
427 else
428 recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter;
429 break;
430
431 case UART_RX_DMA_IT_HT_FLAG:
432 if (counter < uart->dma_rx.remaining_cnt)
433 recv_len = uart->dma_rx.remaining_cnt - counter;
434 break;
435
436 case UART_RX_DMA_IT_TC_FLAG:
437 if(counter >= uart->dma_rx.remaining_cnt)
438 recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter;
439
440 default:
441 break;
442 }
443
444 if (recv_len)
445 {
446 uart->dma_rx.remaining_cnt = counter;
447 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
448 }
449 rt_hw_interrupt_enable(level);
450
451 }
452
453 #endif
454
455 /**
456 * Uart common interrupt process. This need add to uart ISR.
457 *
458 * @param serial serial device
459 */
uart_isr(struct rt_serial_device * serial)460 static void uart_isr(struct rt_serial_device *serial)
461 {
462 struct stm32_uart *uart;
463
464 RT_ASSERT(serial != RT_NULL);
465 uart = rt_container_of(serial, struct stm32_uart, serial);
466
467 /* UART in mode Receiver -------------------------------------------------*/
468 if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
469 (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
470 {
471 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
472 }
473 else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
474 (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
475 {
476 if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
477 {
478 HAL_UART_IRQHandler(&(uart->handle));
479 }
480 else
481 {
482 /* Transmission complete interrupt disable ( CR1 Register) */
483 __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
484 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
485 }
486 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
487 }
488 #ifdef RT_SERIAL_USING_DMA
489 else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
490 && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
491 {
492 dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
493 __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
494 }
495 #endif
496 else
497 {
498 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
499 {
500 __HAL_UART_CLEAR_OREFLAG(&uart->handle);
501 }
502 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
503 {
504 __HAL_UART_CLEAR_NEFLAG(&uart->handle);
505 }
506 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
507 {
508 __HAL_UART_CLEAR_FEFLAG(&uart->handle);
509 }
510 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
511 {
512 __HAL_UART_CLEAR_PEFLAG(&uart->handle);
513 }
514 #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
515 && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
516 && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
517 && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS)
518 #ifdef SOC_SERIES_STM32F3
519 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
520 {
521 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
522 }
523 #else
524 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
525 {
526 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
527 }
528 #endif
529 #endif
530 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
531 {
532 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
533 }
534 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
535 {
536 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
537 }
538 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
539 {
540 UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
541 }
542 }
543 }
544
545 #if defined(BSP_USING_UART1)
USART1_IRQHandler(void)546 void USART1_IRQHandler(void)
547 {
548 /* enter interrupt */
549 rt_interrupt_enter();
550
551 uart_isr(&(uart_obj[UART1_INDEX].serial));
552
553 /* leave interrupt */
554 rt_interrupt_leave();
555 }
556 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
UART1_DMA_RX_IRQHandler(void)557 void UART1_DMA_RX_IRQHandler(void)
558 {
559 /* enter interrupt */
560 rt_interrupt_enter();
561
562 HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
563
564 /* leave interrupt */
565 rt_interrupt_leave();
566 }
567 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
568 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
UART1_DMA_TX_IRQHandler(void)569 void UART1_DMA_TX_IRQHandler(void)
570 {
571 /* enter interrupt */
572 rt_interrupt_enter();
573
574 HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
575
576 /* leave interrupt */
577 rt_interrupt_leave();
578 }
579 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
580 #endif /* BSP_USING_UART1 */
581
582 #if defined(BSP_USING_UART2)
USART2_IRQHandler(void)583 void USART2_IRQHandler(void)
584 {
585 /* enter interrupt */
586 rt_interrupt_enter();
587
588 uart_isr(&(uart_obj[UART2_INDEX].serial));
589
590 /* leave interrupt */
591 rt_interrupt_leave();
592 }
593 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
UART2_DMA_RX_IRQHandler(void)594 void UART2_DMA_RX_IRQHandler(void)
595 {
596 /* enter interrupt */
597 rt_interrupt_enter();
598
599 HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
600
601 /* leave interrupt */
602 rt_interrupt_leave();
603 }
604 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
605 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
UART2_DMA_TX_IRQHandler(void)606 void UART2_DMA_TX_IRQHandler(void)
607 {
608 /* enter interrupt */
609 rt_interrupt_enter();
610
611 HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
612
613 /* leave interrupt */
614 rt_interrupt_leave();
615 }
616 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
617 #endif /* BSP_USING_UART2 */
618
619 #if defined(BSP_USING_UART3)
USART3_IRQHandler(void)620 void USART3_IRQHandler(void)
621 {
622 /* enter interrupt */
623 rt_interrupt_enter();
624
625 uart_isr(&(uart_obj[UART3_INDEX].serial));
626
627 /* leave interrupt */
628 rt_interrupt_leave();
629 }
630 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
UART3_DMA_RX_IRQHandler(void)631 void UART3_DMA_RX_IRQHandler(void)
632 {
633 /* enter interrupt */
634 rt_interrupt_enter();
635
636 HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
637
638 /* leave interrupt */
639 rt_interrupt_leave();
640 }
641 #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
642 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
UART3_DMA_TX_IRQHandler(void)643 void UART3_DMA_TX_IRQHandler(void)
644 {
645 /* enter interrupt */
646 rt_interrupt_enter();
647
648 HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
649
650 /* leave interrupt */
651 rt_interrupt_leave();
652 }
653 #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
654 #endif /* BSP_USING_UART3*/
655
656 #if defined(BSP_USING_UART4)
UART4_IRQHandler(void)657 void UART4_IRQHandler(void)
658 {
659 /* enter interrupt */
660 rt_interrupt_enter();
661
662 uart_isr(&(uart_obj[UART4_INDEX].serial));
663
664 /* leave interrupt */
665 rt_interrupt_leave();
666 }
667 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
UART4_DMA_RX_IRQHandler(void)668 void UART4_DMA_RX_IRQHandler(void)
669 {
670 /* enter interrupt */
671 rt_interrupt_enter();
672
673 HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
674
675 /* leave interrupt */
676 rt_interrupt_leave();
677 }
678 #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
679
680 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
UART4_DMA_TX_IRQHandler(void)681 void UART4_DMA_TX_IRQHandler(void)
682 {
683 /* enter interrupt */
684 rt_interrupt_enter();
685
686 HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
687
688 /* leave interrupt */
689 rt_interrupt_leave();
690 }
691 #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
692 #endif /* BSP_USING_UART4*/
693
694 #if defined(BSP_USING_UART5)
UART5_IRQHandler(void)695 void UART5_IRQHandler(void)
696 {
697 /* enter interrupt */
698 rt_interrupt_enter();
699
700 uart_isr(&(uart_obj[UART5_INDEX].serial));
701
702 /* leave interrupt */
703 rt_interrupt_leave();
704 }
705 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
UART5_DMA_RX_IRQHandler(void)706 void UART5_DMA_RX_IRQHandler(void)
707 {
708 /* enter interrupt */
709 rt_interrupt_enter();
710
711 HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
712
713 /* leave interrupt */
714 rt_interrupt_leave();
715 }
716 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
717 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
UART5_DMA_TX_IRQHandler(void)718 void UART5_DMA_TX_IRQHandler(void)
719 {
720 /* enter interrupt */
721 rt_interrupt_enter();
722
723 HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
724
725 /* leave interrupt */
726 rt_interrupt_leave();
727 }
728 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
729 #endif /* BSP_USING_UART5*/
730
731 #if defined(BSP_USING_UART6)
USART6_IRQHandler(void)732 void USART6_IRQHandler(void)
733 {
734 /* enter interrupt */
735 rt_interrupt_enter();
736
737 uart_isr(&(uart_obj[UART6_INDEX].serial));
738
739 /* leave interrupt */
740 rt_interrupt_leave();
741 }
742 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
UART6_DMA_RX_IRQHandler(void)743 void UART6_DMA_RX_IRQHandler(void)
744 {
745 /* enter interrupt */
746 rt_interrupt_enter();
747
748 HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
749
750 /* leave interrupt */
751 rt_interrupt_leave();
752 }
753 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
754 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
UART6_DMA_TX_IRQHandler(void)755 void UART6_DMA_TX_IRQHandler(void)
756 {
757 /* enter interrupt */
758 rt_interrupt_enter();
759
760 HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
761
762 /* leave interrupt */
763 rt_interrupt_leave();
764 }
765 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
766 #endif /* BSP_USING_UART6*/
767
768 #if defined(BSP_USING_UART7)
UART7_IRQHandler(void)769 void UART7_IRQHandler(void)
770 {
771 /* enter interrupt */
772 rt_interrupt_enter();
773
774 uart_isr(&(uart_obj[UART7_INDEX].serial));
775
776 /* leave interrupt */
777 rt_interrupt_leave();
778 }
779 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
UART7_DMA_RX_IRQHandler(void)780 void UART7_DMA_RX_IRQHandler(void)
781 {
782 /* enter interrupt */
783 rt_interrupt_enter();
784
785 HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
786
787 /* leave interrupt */
788 rt_interrupt_leave();
789 }
790 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
791 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
UART7_DMA_TX_IRQHandler(void)792 void UART7_DMA_TX_IRQHandler(void)
793 {
794 /* enter interrupt */
795 rt_interrupt_enter();
796
797 HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
798
799 /* leave interrupt */
800 rt_interrupt_leave();
801 }
802 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
803 #endif /* BSP_USING_UART7*/
804
805 #if defined(BSP_USING_UART8)
UART8_IRQHandler(void)806 void UART8_IRQHandler(void)
807 {
808 /* enter interrupt */
809 rt_interrupt_enter();
810
811 uart_isr(&(uart_obj[UART8_INDEX].serial));
812
813 /* leave interrupt */
814 rt_interrupt_leave();
815 }
816 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
UART8_DMA_RX_IRQHandler(void)817 void UART8_DMA_RX_IRQHandler(void)
818 {
819 /* enter interrupt */
820 rt_interrupt_enter();
821
822 HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
823
824 /* leave interrupt */
825 rt_interrupt_leave();
826 }
827 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
828 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
UART8_DMA_TX_IRQHandler(void)829 void UART8_DMA_TX_IRQHandler(void)
830 {
831 /* enter interrupt */
832 rt_interrupt_enter();
833
834 HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
835
836 /* leave interrupt */
837 rt_interrupt_leave();
838 }
839 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
840 #endif /* BSP_USING_UART8*/
841
842 #if defined(BSP_USING_LPUART1)
LPUART1_IRQHandler(void)843 void LPUART1_IRQHandler(void)
844 {
845 /* enter interrupt */
846 rt_interrupt_enter();
847
848 uart_isr(&(uart_obj[LPUART1_INDEX].serial));
849
850 /* leave interrupt */
851 rt_interrupt_leave();
852 }
853 #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
LPUART1_DMA_RX_IRQHandler(void)854 void LPUART1_DMA_RX_IRQHandler(void)
855 {
856 /* enter interrupt */
857 rt_interrupt_enter();
858
859 HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
860
861 /* leave interrupt */
862 rt_interrupt_leave();
863 }
864 #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
865 #endif /* BSP_USING_LPUART1*/
866
867 #if defined(SOC_SERIES_STM32G0)
868 #if defined(BSP_USING_UART2)
869 #if defined(STM32G0B1xx) || defined(STM32G0C1xx)
USART2_LPUART2_IRQHandler(void)870 void USART2_LPUART2_IRQHandler(void)
871 {
872 USART2_IRQHandler();
873 }
874 #endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
875 #endif /* defined(BSP_USING_UART2) */
876 #if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
877 || defined(BSP_USING_LPUART1)
878 #if defined(STM32G070xx)
USART3_4_IRQHandler(void)879 void USART3_4_IRQHandler(void)
880 #elif defined(STM32G071xx) || defined(STM32G081xx)
881 void USART3_4_LPUART1_IRQHandler(void)
882 #elif defined(STM32G0B0xx)
883 void USART3_4_5_6_IRQHandler(void)
884 #elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
885 void USART3_4_5_6_LPUART1_IRQHandler(void)
886 #endif /* defined(STM32G070xx) */
887 {
888 #if defined(BSP_USING_UART3)
889 USART3_IRQHandler();
890 #endif
891 #if defined(BSP_USING_UART4)
892 UART4_IRQHandler();
893 #endif
894 #if defined(BSP_USING_UART5)
895 UART5_IRQHandler();
896 #endif
897 #if defined(BSP_USING_UART6)
898 USART6_IRQHandler();
899 #endif
900 #if defined(BSP_USING_LPUART1)
901 LPUART1_IRQHandler();
902 #endif
903 }
904 #endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
905 #if defined(RT_SERIAL_USING_DMA)
UART_DMA_RX_TX_IRQHandler(void)906 void UART_DMA_RX_TX_IRQHandler(void)
907 {
908 #if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
909 UART1_DMA_TX_IRQHandler();
910 #endif
911 #if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
912 UART1_DMA_RX_IRQHandler();
913 #endif
914 #if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
915 UART2_DMA_TX_IRQHandler();
916 #endif
917 #if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
918 UART2_DMA_RX_IRQHandler();
919 #endif
920 }
921 #endif /* defined(RT_SERIAL_USING_DMA) */
922 #endif /* defined(SOC_SERIES_STM32G0) */
923
stm32_uart_get_dma_config(void)924 static void stm32_uart_get_dma_config(void)
925 {
926 #ifdef BSP_USING_UART1
927 uart_obj[UART1_INDEX].uart_dma_flag = 0;
928 #ifdef BSP_UART1_RX_USING_DMA
929 uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
930 static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
931 uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
932 #endif
933 #ifdef BSP_UART1_TX_USING_DMA
934 uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
935 static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
936 uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
937 #endif
938 #endif
939
940 #ifdef BSP_USING_UART2
941 uart_obj[UART2_INDEX].uart_dma_flag = 0;
942 #ifdef BSP_UART2_RX_USING_DMA
943 uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
944 static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
945 uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
946 #endif
947 #ifdef BSP_UART2_TX_USING_DMA
948 uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
949 static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
950 uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
951 #endif
952 #endif
953
954 #ifdef BSP_USING_UART3
955 uart_obj[UART3_INDEX].uart_dma_flag = 0;
956 #ifdef BSP_UART3_RX_USING_DMA
957 uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
958 static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
959 uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
960 #endif
961 #ifdef BSP_UART3_TX_USING_DMA
962 uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
963 static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
964 uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
965 #endif
966 #endif
967
968 #ifdef BSP_USING_UART4
969 uart_obj[UART4_INDEX].uart_dma_flag = 0;
970 #ifdef BSP_UART4_RX_USING_DMA
971 uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
972 static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
973 uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
974 #endif
975 #ifdef BSP_UART4_TX_USING_DMA
976 uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
977 static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
978 uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
979 #endif
980 #endif
981
982 #ifdef BSP_USING_UART5
983 uart_obj[UART5_INDEX].uart_dma_flag = 0;
984 #ifdef BSP_UART5_RX_USING_DMA
985 uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
986 static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
987 uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
988 #endif
989 #ifdef BSP_UART5_TX_USING_DMA
990 uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
991 static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
992 uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
993 #endif
994 #endif
995
996 #ifdef BSP_USING_UART6
997 uart_obj[UART6_INDEX].uart_dma_flag = 0;
998 #ifdef BSP_UART6_RX_USING_DMA
999 uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
1000 static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
1001 uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
1002 #endif
1003 #ifdef BSP_UART6_TX_USING_DMA
1004 uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
1005 static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
1006 uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
1007 #endif
1008 #endif
1009
1010 #ifdef BSP_USING_UART7
1011 uart_obj[UART7_INDEX].uart_dma_flag = 0;
1012 #ifdef BSP_UART7_RX_USING_DMA
1013 uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
1014 static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
1015 uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
1016 #endif
1017 #ifdef BSP_UART7_TX_USING_DMA
1018 uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
1019 static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG;
1020 uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
1021 #endif
1022 #endif
1023
1024 #ifdef BSP_USING_UART8
1025 uart_obj[UART8_INDEX].uart_dma_flag = 0;
1026 #ifdef BSP_UART8_RX_USING_DMA
1027 uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
1028 static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG;
1029 uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
1030 #endif
1031 #ifdef BSP_UART8_TX_USING_DMA
1032 uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
1033 static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG;
1034 uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
1035 #endif
1036 #endif
1037
1038 #ifdef BSP_USING_LPUART1
1039 uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
1040 #ifdef BSP_LPUART1_RX_USING_DMA
1041 uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
1042 static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
1043 uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
1044 #endif
1045 #endif
1046 }
1047
1048 #ifdef RT_SERIAL_USING_DMA
stm32_dma_config(struct rt_serial_device * serial,rt_ubase_t flag)1049 static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
1050 {
1051 struct rt_serial_rx_fifo *rx_fifo;
1052 DMA_HandleTypeDef *DMA_Handle;
1053 struct dma_config *dma_config;
1054 struct stm32_uart *uart;
1055
1056 RT_ASSERT(serial != RT_NULL);
1057 RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
1058 uart = rt_container_of(serial, struct stm32_uart, serial);
1059
1060 if (RT_DEVICE_FLAG_DMA_RX == flag)
1061 {
1062 DMA_Handle = &uart->dma_rx.handle;
1063 dma_config = uart->config->dma_rx;
1064 }
1065 else /* RT_DEVICE_FLAG_DMA_TX == flag */
1066 {
1067 DMA_Handle = &uart->dma_tx.handle;
1068 dma_config = uart->config->dma_tx;
1069 }
1070 LOG_D("%s dma config start", uart->config->name);
1071
1072 {
1073 rt_uint32_t tmpreg = 0x00U;
1074 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
1075 || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
1076 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
1077 SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
1078 tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
1079 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
1080 || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
1081 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
1082 SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
1083 tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
1084 #elif defined(SOC_SERIES_STM32MP1)
1085 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
1086 SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
1087 tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
1088 #endif
1089
1090 #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
1091 /* enable DMAMUX clock for L4+ and G4 */
1092 __HAL_RCC_DMAMUX1_CLK_ENABLE();
1093 #elif defined(SOC_SERIES_STM32MP1)
1094 __HAL_RCC_DMAMUX_CLK_ENABLE();
1095 #endif
1096
1097 UNUSED(tmpreg); /* To avoid compiler warnings */
1098 }
1099
1100 if (RT_DEVICE_FLAG_DMA_RX == flag)
1101 {
1102 __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
1103 }
1104 else if (RT_DEVICE_FLAG_DMA_TX == flag)
1105 {
1106 __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
1107 }
1108
1109 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
1110 DMA_Handle->Instance = dma_config->Instance;
1111 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
1112 DMA_Handle->Instance = dma_config->Instance;
1113 DMA_Handle->Init.Channel = dma_config->channel;
1114 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
1115 || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
1116 DMA_Handle->Instance = dma_config->Instance;
1117 DMA_Handle->Init.Request = dma_config->request;
1118 #endif
1119 DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
1120 DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
1121 DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
1122 DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
1123
1124 if (RT_DEVICE_FLAG_DMA_RX == flag)
1125 {
1126 DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
1127 DMA_Handle->Init.Mode = DMA_CIRCULAR;
1128 }
1129 else if (RT_DEVICE_FLAG_DMA_TX == flag)
1130 {
1131 DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
1132 DMA_Handle->Init.Mode = DMA_NORMAL;
1133 }
1134
1135 DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
1136 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
1137 DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
1138 #endif
1139 if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
1140 {
1141 RT_ASSERT(0);
1142 }
1143
1144 if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
1145 {
1146 RT_ASSERT(0);
1147 }
1148
1149 /* enable interrupt */
1150 if (flag == RT_DEVICE_FLAG_DMA_RX)
1151 {
1152 rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
1153 /* Start DMA transfer */
1154 if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
1155 {
1156 /* Transfer error in reception process */
1157 RT_ASSERT(0);
1158 }
1159 CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
1160 __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
1161 }
1162
1163 /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
1164 HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
1165 HAL_NVIC_EnableIRQ(dma_config->dma_irq);
1166
1167 HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
1168 HAL_NVIC_EnableIRQ(uart->config->irq_type);
1169
1170 LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
1171 LOG_D("%s dma config done", uart->config->name);
1172 }
1173
1174 /**
1175 * @brief UART error callbacks
1176 * @param huart: UART handle
1177 * @note This example shows a simple way to report transfer error, and you can
1178 * add your own implementation.
1179 * @retval None
1180 */
HAL_UART_ErrorCallback(UART_HandleTypeDef * huart)1181 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
1182 {
1183 RT_ASSERT(huart != NULL);
1184 struct stm32_uart *uart = (struct stm32_uart *)huart;
1185 LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
1186 UNUSED(uart);
1187 }
1188
1189 /**
1190 * @brief Rx Transfer completed callback
1191 * @param huart: UART handle
1192 * @note This example shows a simple way to report end of DMA Rx transfer, and
1193 * you can add your own implementation.
1194 * @retval None
1195 */
HAL_UART_RxCpltCallback(UART_HandleTypeDef * huart)1196 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
1197 {
1198 struct stm32_uart *uart;
1199 RT_ASSERT(huart != NULL);
1200 uart = (struct stm32_uart *)huart;
1201 dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
1202 }
1203
1204 /**
1205 * @brief Rx Half transfer completed callback
1206 * @param huart: UART handle
1207 * @note This example shows a simple way to report end of DMA Rx Half transfer,
1208 * and you can add your own implementation.
1209 * @retval None
1210 */
HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef * huart)1211 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
1212 {
1213 struct stm32_uart *uart;
1214 RT_ASSERT(huart != NULL);
1215 uart = (struct stm32_uart *)huart;
1216 dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG);
1217 }
1218
_dma_tx_complete(struct rt_serial_device * serial)1219 static void _dma_tx_complete(struct rt_serial_device *serial)
1220 {
1221 struct stm32_uart *uart;
1222 rt_size_t trans_total_index;
1223 rt_base_t level;
1224
1225 RT_ASSERT(serial != RT_NULL);
1226 uart = rt_container_of(serial, struct stm32_uart, serial);
1227
1228 level = rt_hw_interrupt_disable();
1229 trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
1230 rt_hw_interrupt_enable(level);
1231
1232 if (trans_total_index == 0)
1233 {
1234 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
1235 }
1236 }
1237
1238 /**
1239 * @brief HAL_UART_TxCpltCallback
1240 * @param huart: UART handle
1241 * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
1242 * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
1243 * @retval None
1244 */
HAL_UART_TxCpltCallback(UART_HandleTypeDef * huart)1245 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
1246 {
1247 struct stm32_uart *uart;
1248 RT_ASSERT(huart != NULL);
1249 uart = (struct stm32_uart *)huart;
1250 _dma_tx_complete(&uart->serial);
1251 }
1252 #endif /* RT_SERIAL_USING_DMA */
1253
1254 static const struct rt_uart_ops stm32_uart_ops =
1255 {
1256 .configure = stm32_configure,
1257 .control = stm32_control,
1258 .putc = stm32_putc,
1259 .getc = stm32_getc,
1260 .dma_transmit = stm32_dma_transmit
1261 };
1262
rt_hw_usart_init(void)1263 int rt_hw_usart_init(void)
1264 {
1265 struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
1266 rt_err_t result = 0;
1267
1268 stm32_uart_get_dma_config();
1269
1270 for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(struct stm32_uart); i++)
1271 {
1272 /* init UART object */
1273 uart_obj[i].config = &uart_config[i];
1274 uart_obj[i].serial.ops = &stm32_uart_ops;
1275 uart_obj[i].serial.config = config;
1276
1277 /* register UART device */
1278 result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
1279 RT_DEVICE_FLAG_RDWR
1280 | RT_DEVICE_FLAG_INT_RX
1281 | RT_DEVICE_FLAG_INT_TX
1282 | uart_obj[i].uart_dma_flag
1283 , NULL);
1284 RT_ASSERT(result == RT_EOK);
1285 }
1286
1287 return result;
1288 }
1289
1290 #endif /* RT_USING_SERIAL */
1291