1<!DOCTYPE html> 2<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en"> 3<head> 4 <meta charset="utf-8" /> 5 <meta name="generator" content="pandoc" /> 6 <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" /> 7 <title>Release Notes for STM32L1xx CMSIS</title> 8 <style type="text/css"> 9 code{white-space: pre-wrap;} 10 span.smallcaps{font-variant: small-caps;} 11 span.underline{text-decoration: underline;} 12 div.column{display: inline-block; vertical-align: top; width: 50%;} 13 </style> 14 <link rel="stylesheet" href="_htmresc/mini-st.css" /> 15 <!--[if lt IE 9]> 16 <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script> 17 <![endif]--> 18</head> 19<body> 20<div class="row"> 21<div class="col-sm-12 col-lg-4"> 22<div class="card fluid"> 23<div class="sectione dark"> 24<center> 25<h1 id="release-notes-for-stm32l1xx-cmsis"><small>Release Notes for</small> <mark>STM32L1xx CMSIS</mark></h1> 26<p>Copyright © 2009-2018 ARM Limited - STMicroelectronics<br /> 27</p> 28<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a> 29</center> 30</div> 31</div> 32<h1 id="purpose">Purpose</h1> 33<p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p> 34<ul> 35<li>STM32L100xx devices</li> 36<li>STM32L151xx devices</li> 37<li>STM32L152xx devices</li> 38<li>STM32L162xx devices</li> 39</ul> 40<p>This driver is composed of the descriptions of the registers under “Include” directory.</p> 41<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p> 42<ul> 43<li>Templates/system_stm32l1xx.c contains the initialization code referred as SystemInit.</li> 44<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li> 45<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li> 46</ul> 47</div> 48<div class="col-sm-12 col-lg-8"> 49<h1 id="update-history">Update History</h1> 50<div class="collapse"> 51<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V2.3.2 / 21-May-2021</label> 52<div> 53<h2 id="main-changes">Main Changes</h2> 54<h3 id="maintenance-release">Maintenance release</h3> 55<h2 id="contents">Contents</h2> 56<ul> 57<li>Improve GCC startup files robustness.</li> 58<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li> 59<li>Add atomic register access macros.</li> 60<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li> 61<li>Remove bit definition related to PF and PG ports from unsupported devices (L1xxxB devices).</li> 62<li>Fix SYSCFG_EXTICR1_EXTI3_PF and SYSCFG_EXTICR1_EXTI3_PG defines values.</li> 63<li>Update the hal_flash.h file to correctly support the FLASH_SIZE of cat.2 devices.</li> 64</ul> 65</div> 66</div> 67<div class="collapse"> 68<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.3.1 / 24-June-2020</label> 69<div> 70<h2 id="main-changes-1">Main Changes</h2> 71<h3 id="maintenance-release-1">Maintenance release</h3> 72<h2 id="contents-1">Contents</h2> 73<ul> 74<li>All header files 75<ul> 76<li>Remove NVIC CMSIS bits definitions to avoid duplication with CMSIS Core V5.x</li> 77<li>Remove GPIOx BRR register from GPIO structure and bit definitions when not supported</li> 78<li>Add ADC VREFINT/TEMPSENSOR addresses definitions in line with products datasheets: 79<ul> 80<li>VREFINT_CAL_ADDR_CMSIS</li> 81<li>TEMPSENSOR_CAL1_ADDR_CMSIS</li> 82<li>TEMPSENSOR_CAL2_ADDR_CMSIS</li> 83</ul></li> 84<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro</li> 85<li>Update IS_TIM_MASTER_INSTANCE with all supported instances.</li> 86</ul></li> 87<li>system_stm32l1xx.c file 88<ul> 89<li>Update SystemInit() API to don’t reset RCC registers to its reset values</li> 90</ul></li> 91</ul> 92</div> 93</div> 94<div class="collapse"> 95<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.3.0 / 05-April-2019</label> 96<div> 97<h2 id="main-changes-2">Main Changes</h2> 98<h3 id="maintenance-release-2">Maintenance release</h3> 99<h2 id="contents-2">Contents</h2> 100<ul> 101<li>stm32l0xx.h 102<ul> 103<li>Align ErrorStatus typedef to common error handling</li> 104</ul></li> 105<li>startup_stm32l1xxxxx.s 106<ul> 107<li>Update header of startup files to remove build error with ARM compiler.</li> 108</ul></li> 109<li>Updated Update CMSIS Devices compliancy with MISRA C 2012 rules 110<ul> 111<li>Rule-10.6: Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses</li> 112</ul></li> 113<li>Update CMSIS device description files according to latest version of HAL/LL drivers 114<ul> 115<li>Correct definitions for USB_COUNT3_TX_0 and USB_COUNT3_TX_1 registers</li> 116<li>Add IS_PCD_ALL_INSTANCE definition</li> 117<li>Add IS_TIM_SYNCHRO_INSTANCE macro definition</li> 118<li>Update macros definition for TIM instances</li> 119</ul></li> 120</ul> 121</div> 122</div> 123<div class="collapse"> 124<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V2.2.3 / 12-January-2018</label> 125<div> 126<h2 id="main-changes-3">Main Changes</h2> 127<h3 id="patch-release">Patch release</h3> 128<h2 id="contents-3">Contents</h2> 129<ul> 130<li>Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</li> 131</ul> 132</div> 133</div> 134<div class="collapse"> 135<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V2.2.2 / 25-August-2017</label> 136<div> 137<h2 id="main-changes-4">Main Changes</h2> 138<h3 id="maintenance-release-3">Maintenance release</h3> 139<h2 id="contents-4">Contents</h2> 140<ul> 141<li>Removed DATE and VERSION fields from header files.</li> 142</ul> 143</div> 144</div> 145<div class="collapse"> 146<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V2.2.1 / 21-April-2017</label> 147<div> 148<h2 id="main-changes-5">Main Changes</h2> 149<h3 id="maintenance-release-4">Maintenance release</h3> 150<h2 id="contents-5">Contents</h2> 151<ul> 152<li>Update CMSIS Devices compliancy with MISRA C 2004 rules: 153<ul> 154<li>MISRA C 2004 rule 10.6 (‘U’ suffix applied to all constants of ‘unsigned’ type)</li> 155<li>Update system_stm32l1xx.h/.c files.</li> 156</ul></li> 157<li>Align Bit definitions for SCB_CFSR register to be compliant with CMSIS Core V4.x and V5.x.</li> 158<li>Rename RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.</li> 159<li>Rename GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.</li> 160</ul> 161</div> 162</div> 163<div class="collapse"> 164<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V2.2.0 / 01-July-2016</label> 165<div> 166<h2 id="main-changes-6">Main Changes</h2> 167<h3 id="maintenance-release-5">Maintenance release</h3> 168<h2 id="contents-6">Contents</h2> 169<ul> 170<li>Add macros _Pos and _Msk for each constants. 171<ul> 172<li>For instance: 173<ul> 174<li>#define ADC_LTR_LT ((uint32_t)0x00000FFFU)</li> 175</ul></li> 176<li>Is now provided as: 177<ul> 178<li>#define ADC_LTR_LT_Pos (0U)</li> 179<li>#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos)</li> 180<li>#define ADC_LTR_LT ADC_LTR_LT_Msk</li> 181</ul></li> 182</ul></li> 183<li>IS_I2S_ALL_INSTANCE is now SPI2 and SPI3 instead of SPI1 and SPI2.</li> 184<li>Update the TIM_ARR_ARR and TIM_CNT_CNT as they support the 32 bit counter feature.</li> 185<li>Add macro IS_TIM_ETR_INSTANCE.</li> 186<li>Add RI_ASCR2_GR6_x with x = 1,2,3,4 if applicable.</li> 187<li>Add macro IS_SMBUS_ALL_INSTANCE.</li> 188<li>Set default value for SystemCoreClock to 2097000 instead of 32000000.</li> 189<li>Correct the presence of TIM9 for some devices inside various TIMER macros.</li> 190</ul> 191</div> 192</div> 193<div class="collapse"> 194<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V2.1.3 / 04-March-2016</label> 195<div> 196<h2 id="main-changes-7">Main Changes</h2> 197<h3 id="maintenance-release-6">Maintenance release</h3> 198<h2 id="contents-7">Contents</h2> 199<ul> 200<li>Add HardFault_IRQn.</li> 201<li>Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba.</li> 202<li>Align bits naming on all stm32 families (ex: WWDG_CFR_WDGTB0 -> WWDG_CFR_WDGTB_0).</li> 203<li>Rename RCC_CFGR_MCO_DIVx to RCC_CFGR_MCOPRE_DIVx</li> 204<li>Align Bits naming on all stm32 families (ex: EXTI_IMR_MR0 –> EXTI_IMR_IM0)</li> 205<li>Update .icf file to correct empty linker ROM Start/End menu, under IAR, for stm32l151xdx, stm32l152xdx and stm32l162xdx.</li> 206<li>Rename RCC_CFGR_MCO_x to RCC_CFGR_MCOSEL_x to be aligned with Reference Manual.</li> 207<li>Update CMSIS drivers to apply MISRA C 2004 rule 10.6. (Use U postfix)</li> 208<li>Add defines FLASHSIZE_BASE and UID_BASE</li> 209<li>ADC common instance standardization (new define ADC1_COMMON)</li> 210<li>Remove bit GPIO_BRR_BR_x from Cat1 to Cat2 devices</li> 211<li>Literals “ADC_SMPR1_SMP27, ADC_SMPR1_SMP28, ADC_SMPR1_SMP29” are available on Cat4, Cat5 only.</li> 212<li>Add DMA_CNDTR_NDT, DMA_CPAR_PA and DMA_CMAR_MA definitions present on other stm32 families.</li> 213<li>Add defines to trig feature inside source code based on CMSIS content: 214<ul> 215<li>RTC_TAMPER1_SUPPORT</li> 216<li>RTC_TAMPER2_SUPPORT</li> 217<li>RTC_TAMPER3_SUPPORT</li> 218<li>RTC_BACKUP_SUPPORT</li> 219<li>RTC_WAKEUP_SUPPORT</li> 220<li>RTC_SMOOTHCALIB_SUPPORT</li> 221<li>RTC_SUBSECOND_SUPPORT.</li> 222<li>PWR_PVD_SUPPORT</li> 223</ul></li> 224<li>Set CMSIS variables PLLMulTable, AHBPrescTable and APBPrescTable as external in system_stm32l1xx.h.</li> 225<li>Bit 23 of all EXTI registers (IMR, EMR, …) is not supported on Cat 1 & 2.</li> 226<li>Correct a wrong values for RI_ASCR1_CH_27 to RI_ASCR1_CH_30</li> 227<li>Add defines for LCD capacitance</li> 228<li>Suppress SPI1 from I2S_ALL_INSTANCE</li> 229</ul> 230</div> 231</div> 232<div class="collapse"> 233<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V2.1.2 / 09-October-2015</label> 234<div> 235<h2 id="main-changes-8">Main Changes</h2> 236<h3 id="maintenance-release-7">Maintenance release</h3> 237<h2 id="contents-8">Contents</h2> 238<ul> 239<li>Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation.</li> 240<li>IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure.</li> 241<li>Added TIM10 and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE).</li> 242<li>Renaming USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other bits.</li> 243<li>Renaming USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this register.</li> 244</ul> 245</div> 246</div> 247<div class="collapse"> 248<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V2.1.1 / 31-March-2015</label> 249<div> 250<h2 id="main-changes-9">Main Changes</h2> 251<h3 id="maintenance-release-8">Maintenance release</h3> 252<h2 id="contents-9">Contents</h2> 253<ul> 254<li>Ensure compliancy w/ C++</li> 255<li>Minor update on Timer assert.</li> 256<li>Adding IS_AES_ALL_INSTANCE macro for product with AES.</li> 257</ul> 258</div> 259</div> 260<div class="collapse"> 261<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V2.1.0 / 06-February-2015</label> 262<div> 263<h2 id="main-changes-10">Main Changes</h2> 264<h3 id="maintenance-release-9">Maintenance release</h3> 265<h2 id="contents-10">Contents</h2> 266<ul> 267<li>Add CMSIS files for new STM32L1 e<strong>X</strong>tended Devices : <strong>STM32L151xDX, STM32L152xDX and STM32L162xDX</strong></li> 268</ul> 269</div> 270</div> 271<div class="collapse"> 272<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V2.0.0 / 05-September-2014</label> 273<div> 274<h2 id="main-changes-11">Main Changes</h2> 275<h3 id="maintenance-release-10">Maintenance release</h3> 276<h2 id="contents-11">Contents</h2> 277<ul> 278<li>Update based on STM32Cube specification</li> 279</ul> 280<h2 id="other-compatibilities">Other compatibilities</h2> 281<ul> 282<li>This version has to be used only with <strong>STM32CubeL1</strong> based development</li> 283</ul> 284</div> 285</div> 286</div> 287</div> 288<footer class="sticky"> 289For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a> 290</footer> 291</body> 292</html> 293
