1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© Copyright(c) 2017 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef __STM32L1xx_LL_BUS_H
39 #define __STM32L1xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32l1xx.h"
47
48 /** @addtogroup STM32L1xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
75 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
76 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
77 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
78 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
79 #if defined(GPIOE)
80 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
81 #endif/*GPIOE*/
82 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
83 #if defined(GPIOF)
84 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
85 #endif/*GPIOF*/
86 #if defined(GPIOG)
87 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
88 #endif/*GPIOG*/
89 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN
90 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
91 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
92 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
93 #if defined(DMA2)
94 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
95 #endif/*DMA2*/
96 #if defined(AES)
97 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
98 #endif/*AES*/
99 #if defined(FSMC_Bank1)
100 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
101 #endif/*FSMC_Bank1*/
102 /**
103 * @}
104 */
105
106 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
107 * @{
108 */
109 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
110 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
111 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
112 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
113 #if defined(TIM5)
114 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
115 #endif /*TIM5*/
116 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
117 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
118 #if defined(LCD)
119 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN
120 #endif /*LCD*/
121 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
122 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
123 #if defined(SPI3)
124 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
125 #endif /*SPI3*/
126 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
127 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
128 #if defined(UART4)
129 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
130 #endif /*UART4*/
131 #if defined(UART5)
132 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
133 #endif /*UART5*/
134 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
135 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
136 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
137 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
138 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
139 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN
140 #if defined(OPAMP)
141 /* Note: Peripherals COMP and OPAMP share the same clock domain */
142 #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP
143 #endif
144 /**
145 * @}
146 */
147
148 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
149 * @{
150 */
151 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
152 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
153 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
154 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
155 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
156 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
157 #if defined(SDIO)
158 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
159 #endif /*SDIO*/
160 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
161 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
162 /**
163 * @}
164 */
165
166 /**
167 * @}
168 */
169
170 /* Exported macro ------------------------------------------------------------*/
171
172 /* Exported functions --------------------------------------------------------*/
173 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
174 * @{
175 */
176
177 /** @defgroup BUS_LL_EF_AHB1 AHB1
178 * @{
179 */
180
181 /**
182 * @brief Enable AHB1 peripherals clock.
183 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
184 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
185 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
186 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
187 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
188 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
189 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
190 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
191 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
192 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
193 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
194 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
195 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
196 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
197 * @param Periphs This parameter can be a combination of the following values:
198 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
199 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
200 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
201 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
202 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
203 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
204 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
205 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
206 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
207 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
208 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
209 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
210 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
211 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
212 *
213 * (*) value not defined in all devices.
214 * @retval None
215 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)216 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
217 {
218 __IO uint32_t tmpreg;
219 SET_BIT(RCC->AHBENR, Periphs);
220 /* Delay after an RCC peripheral clock enabling */
221 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
222 (void)tmpreg;
223 }
224
225 /**
226 * @brief Check if AHB1 peripheral clock is enabled or not
227 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
228 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
229 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
230 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
231 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
232 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
233 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
234 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
235 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
236 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
237 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
238 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
239 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
240 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
241 * @param Periphs This parameter can be a combination of the following values:
242 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
243 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
244 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
245 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
246 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
247 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
248 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
249 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
250 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
251 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
252 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
253 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
254 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
255 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
256 *
257 * (*) value not defined in all devices.
258 * @retval State of Periphs (1 or 0).
259 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)260 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
261 {
262 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);
263 }
264
265 /**
266 * @brief Disable AHB1 peripherals clock.
267 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
268 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
269 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
270 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
271 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
272 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
273 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
274 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
275 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
276 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
277 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
278 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
279 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
280 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
281 * @param Periphs This parameter can be a combination of the following values:
282 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
283 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
284 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
285 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
286 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
287 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
288 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
289 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
290 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
291 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
292 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
293 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
294 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
295 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
296 *
297 * (*) value not defined in all devices.
298 * @retval None
299 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)300 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
301 {
302 CLEAR_BIT(RCC->AHBENR, Periphs);
303 }
304
305 /**
306 * @brief Force AHB1 peripherals reset.
307 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
308 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
309 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
310 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
311 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
312 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
313 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
314 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
315 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
316 * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n
317 * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
318 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
319 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
320 * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset
321 * @param Periphs This parameter can be a combination of the following values:
322 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
323 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
324 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
325 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
326 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
327 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
328 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
329 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
330 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
331 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
332 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
333 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
334 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
335 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
336 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
337 *
338 * (*) value not defined in all devices.
339 * @retval None
340 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)341 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
342 {
343 SET_BIT(RCC->AHBRSTR, Periphs);
344 }
345
346 /**
347 * @brief Release AHB1 peripherals reset.
348 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
349 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
350 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
351 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
352 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
353 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
354 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
355 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
356 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
357 * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n
358 * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
359 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
360 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
361 * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset
362 * @param Periphs This parameter can be a combination of the following values:
363 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
364 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
365 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
366 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
367 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
368 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
369 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
370 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
371 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
372 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
373 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
374 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
375 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
376 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
377 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
378 *
379 * (*) value not defined in all devices.
380 * @retval None
381 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)382 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
383 {
384 CLEAR_BIT(RCC->AHBRSTR, Periphs);
385 }
386
387 /**
388 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
389 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n
390 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n
391 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n
392 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n
393 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n
394 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n
395 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n
396 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n
397 * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
398 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
399 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
400 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
401 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
402 * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n
403 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep
404 * @param Periphs This parameter can be a combination of the following values:
405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
412 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
413 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
414 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
415 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
416 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
417 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
418 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
419 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
420 *
421 * (*) value not defined in all devices.
422 * @retval None
423 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)424 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
425 {
426 __IO uint32_t tmpreg;
427 SET_BIT(RCC->AHBLPENR, Periphs);
428 /* Delay after an RCC peripheral clock enabling */
429 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
430 (void)tmpreg;
431 }
432
433 /**
434 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
435 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n
436 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n
437 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n
438 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n
439 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n
440 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n
441 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n
442 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n
443 * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
444 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
445 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
446 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
447 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
448 * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n
449 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep
450 * @param Periphs This parameter can be a combination of the following values:
451 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
452 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
453 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
454 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
456 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
457 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
458 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
459 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
460 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
461 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
463 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
464 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
466 *
467 * (*) value not defined in all devices.
468 * @retval None
469 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)470 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
471 {
472 CLEAR_BIT(RCC->AHBLPENR, Periphs);
473 }
474
475 /**
476 * @}
477 */
478
479 /** @defgroup BUS_LL_EF_APB1 APB1
480 * @{
481 */
482
483 /**
484 * @brief Enable APB1 peripherals clock.
485 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
486 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
487 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
488 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
489 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
490 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
491 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
492 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
493 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
494 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
495 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
496 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
497 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
498 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
499 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
500 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
501 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
502 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
503 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
504 * APB1ENR COMPEN LL_APB1_GRP1_EnableClock
505 * @param Periphs This parameter can be a combination of the following values:
506 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
507 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
512 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
513 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
514 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
515 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
516 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
517 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
518 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
519 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
520 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
521 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
522 * @arg @ref LL_APB1_GRP1_PERIPH_USB
523 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
524 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
525 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
526 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
527 *
528 * (*) value not defined in all devices.
529 * @retval None
530 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)531 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
532 {
533 __IO uint32_t tmpreg;
534 SET_BIT(RCC->APB1ENR, Periphs);
535 /* Delay after an RCC peripheral clock enabling */
536 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
537 (void)tmpreg;
538 }
539
540 /**
541 * @brief Check if APB1 peripheral clock is enabled or not
542 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
543 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
544 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
545 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
546 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
547 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
548 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
549 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
550 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
551 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
552 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
553 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
554 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
555 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
556 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
557 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
558 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
559 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
560 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
561 * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock
562 * @param Periphs This parameter can be a combination of the following values:
563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
565 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
566 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
567 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
568 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
569 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
570 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
571 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
572 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
573 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
574 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
575 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
576 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
577 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
578 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
579 * @arg @ref LL_APB1_GRP1_PERIPH_USB
580 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
581 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
582 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
583 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
584 *
585 * (*) value not defined in all devices.
586 * @retval State of Periphs (1 or 0).
587 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)588 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
589 {
590 return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Disable APB1 peripherals clock.
595 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
596 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
597 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
598 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
599 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
600 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
601 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
602 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
603 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
604 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
605 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
606 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
607 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
608 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
609 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
610 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
611 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
612 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
613 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
614 * APB1ENR COMPEN LL_APB1_GRP1_DisableClock
615 * @param Periphs This parameter can be a combination of the following values:
616 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
622 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
623 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
624 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
625 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
626 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
627 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
628 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
629 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
630 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
631 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
632 * @arg @ref LL_APB1_GRP1_PERIPH_USB
633 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
634 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
635 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
636 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
637 *
638 * (*) value not defined in all devices.
639 * @retval None
640 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)641 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
642 {
643 CLEAR_BIT(RCC->APB1ENR, Periphs);
644 }
645
646 /**
647 * @brief Force APB1 peripherals reset.
648 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
649 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
650 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
651 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
652 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
653 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
654 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
655 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
656 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
657 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
658 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
659 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
660 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
661 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
662 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
663 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
664 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
665 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
666 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
667 * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset
668 * @param Periphs This parameter can be a combination of the following values:
669 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
670 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
671 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
672 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
673 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
674 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
675 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
676 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
677 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
678 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
679 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
680 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
681 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
682 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
683 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
684 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
685 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
686 * @arg @ref LL_APB1_GRP1_PERIPH_USB
687 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
688 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
689 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
690 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
691 *
692 * (*) value not defined in all devices.
693 * @retval None
694 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)695 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
696 {
697 SET_BIT(RCC->APB1RSTR, Periphs);
698 }
699
700 /**
701 * @brief Release APB1 peripherals reset.
702 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
703 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
704 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
705 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
706 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
707 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
708 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
709 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
710 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
711 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
712 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
713 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
714 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
715 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
716 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
717 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
718 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
719 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
720 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
721 * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset
722 * @param Periphs This parameter can be a combination of the following values:
723 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
724 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
725 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
726 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
727 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
728 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
729 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
730 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
731 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
732 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
733 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
734 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
735 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
736 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
737 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
738 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
739 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
740 * @arg @ref LL_APB1_GRP1_PERIPH_USB
741 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
742 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
743 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
744 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
745 *
746 * (*) value not defined in all devices.
747 * @retval None
748 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)749 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
750 {
751 CLEAR_BIT(RCC->APB1RSTR, Periphs);
752 }
753
754 /**
755 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
756 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
757 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
758 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
759 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
760 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
761 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
762 * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n
763 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
764 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
765 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
766 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
767 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
768 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
769 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
770 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
771 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
772 * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n
773 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n
774 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n
775 * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep
776 * @param Periphs This parameter can be a combination of the following values:
777 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
778 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
779 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
780 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
781 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
782 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
783 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
784 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
785 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
786 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
787 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
788 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
789 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
790 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
791 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
792 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
793 * @arg @ref LL_APB1_GRP1_PERIPH_USB
794 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
795 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
796 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
797 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
798 *
799 * (*) value not defined in all devices.
800 * @retval None
801 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)802 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
803 {
804 __IO uint32_t tmpreg;
805 SET_BIT(RCC->APB1LPENR, Periphs);
806 /* Delay after an RCC peripheral clock enabling */
807 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
808 (void)tmpreg;
809 }
810
811 /**
812 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
813 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
814 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
815 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
816 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
817 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
818 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
819 * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n
820 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
821 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
822 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
823 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
824 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
825 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
826 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
827 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
828 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
829 * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n
830 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n
831 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n
832 * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep
833 * @param Periphs This parameter can be a combination of the following values:
834 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
835 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
836 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
837 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
838 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
839 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
840 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
841 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
842 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
843 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
844 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
845 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
846 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
847 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
848 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
849 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
850 * @arg @ref LL_APB1_GRP1_PERIPH_USB
851 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
852 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
853 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
854 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
855 *
856 * (*) value not defined in all devices.
857 * @retval None
858 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)859 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
860 {
861 CLEAR_BIT(RCC->APB1LPENR, Periphs);
862 }
863
864 /**
865 * @}
866 */
867
868 /** @defgroup BUS_LL_EF_APB2 APB2
869 * @{
870 */
871
872 /**
873 * @brief Enable APB2 peripherals clock.
874 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
875 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
876 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
877 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
878 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
879 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
880 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
881 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
882 * @param Periphs This parameter can be a combination of the following values:
883 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
885 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
886 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
887 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
888 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
889 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
890 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
891 *
892 * (*) value not defined in all devices.
893 * @retval None
894 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)895 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
896 {
897 __IO uint32_t tmpreg;
898 SET_BIT(RCC->APB2ENR, Periphs);
899 /* Delay after an RCC peripheral clock enabling */
900 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
901 (void)tmpreg;
902 }
903
904 /**
905 * @brief Check if APB2 peripheral clock is enabled or not
906 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
907 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
908 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
909 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
910 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
911 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
912 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
913 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
914 * @param Periphs This parameter can be a combination of the following values:
915 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
916 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
917 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
918 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
919 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
920 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
921 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
922 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
923 *
924 * (*) value not defined in all devices.
925 * @retval State of Periphs (1 or 0).
926 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)927 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
928 {
929 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
930 }
931
932 /**
933 * @brief Disable APB2 peripherals clock.
934 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
935 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
936 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
937 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
938 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
939 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
940 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
941 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
942 * @param Periphs This parameter can be a combination of the following values:
943 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
944 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
945 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
946 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
947 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
948 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
949 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
950 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
951 *
952 * (*) value not defined in all devices.
953 * @retval None
954 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)955 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
956 {
957 CLEAR_BIT(RCC->APB2ENR, Periphs);
958 }
959
960 /**
961 * @brief Force APB2 peripherals reset.
962 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
963 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
964 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
965 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
966 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
967 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
968 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
969 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
970 * @param Periphs This parameter can be a combination of the following values:
971 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
972 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
973 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
974 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
975 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
976 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
977 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
978 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
979 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
980 *
981 * (*) value not defined in all devices.
982 * @retval None
983 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)984 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
985 {
986 SET_BIT(RCC->APB2RSTR, Periphs);
987 }
988
989 /**
990 * @brief Release APB2 peripherals reset.
991 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
992 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
993 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
994 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
995 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
996 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
997 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
998 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
999 * @param Periphs This parameter can be a combination of the following values:
1000 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1001 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1002 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1003 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1004 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1005 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1006 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1007 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1008 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1009 *
1010 * (*) value not defined in all devices.
1011 * @retval None
1012 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1013 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1014 {
1015 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1016 }
1017
1018 /**
1019 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
1020 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n
1021 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
1022 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n
1023 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n
1024 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n
1025 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n
1026 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
1027 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
1028 * @param Periphs This parameter can be a combination of the following values:
1029 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1030 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1031 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1032 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1033 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1034 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1035 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1036 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1037 *
1038 * (*) value not defined in all devices.
1039 * @retval None
1040 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)1041 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
1042 {
1043 __IO uint32_t tmpreg;
1044 SET_BIT(RCC->APB2LPENR, Periphs);
1045 /* Delay after an RCC peripheral clock enabling */
1046 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
1047 (void)tmpreg;
1048 }
1049
1050 /**
1051 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
1052 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n
1053 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
1054 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n
1055 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n
1056 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n
1057 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n
1058 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
1059 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
1060 * @param Periphs This parameter can be a combination of the following values:
1061 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1062 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1063 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1064 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1065 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1066 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1067 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1068 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1069 *
1070 * (*) value not defined in all devices.
1071 * @retval None
1072 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)1073 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
1074 {
1075 CLEAR_BIT(RCC->APB2LPENR, Periphs);
1076 }
1077
1078 /**
1079 * @}
1080 */
1081
1082
1083 /**
1084 * @}
1085 */
1086
1087 /**
1088 * @}
1089 */
1090
1091 #endif /* defined(RCC) */
1092
1093 /**
1094 * @}
1095 */
1096
1097 #ifdef __cplusplus
1098 }
1099 #endif
1100
1101 #endif /* __STM32L1xx_LL_BUS_H */
1102
1103 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1104