1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-11-06     SummerGift   first version
9  */
10 
11 #include "board.h"
12 
SystemClock_Config(void)13 void SystemClock_Config(void)
14 {
15   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
16   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
17   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
18 
19   /**Supply configuration update enable
20   */
21   MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
22   /**Configure the main internal regulator output voltage
23   */
24   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
25 
26   while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY)
27   {
28 
29   }
30   /**Initializes the CPU, AHB and APB busses clocks
31   */
32   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
33   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
34   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
35   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
36   RCC_OscInitStruct.PLL.PLLM = 5;
37   RCC_OscInitStruct.PLL.PLLN = 160;
38   RCC_OscInitStruct.PLL.PLLP = 2;
39   RCC_OscInitStruct.PLL.PLLQ = 2;
40   RCC_OscInitStruct.PLL.PLLR = 2;
41   RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
42   RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
43   RCC_OscInitStruct.PLL.PLLFRACN = 0;
44   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
45   {
46     Error_Handler();
47   }
48   /**Initializes the CPU, AHB and APB busses clocks
49   */
50   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
51                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
52                               |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
53   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
54   RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
55   RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
56   RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
57   RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
58   RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
59   RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
60 
61   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
62   {
63     Error_Handler();
64   }
65   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
66   PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
67   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
68   {
69     Error_Handler();
70   }
71 }
72 
73