1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 SummerGift first version 9 * 2019-04-09 WillianChan add stm32f469-st-disco bsp 10 * 2020-06-20 thread-liu add stm32mp157-dk1 bsp 11 */ 12 13 #include "board.h" 14 15 /** 16 * @brief System Clock Configuration 17 * @retval None 18 */ SystemClock_Config(void)19void SystemClock_Config(void) 20 { 21 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 22 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 23 24 /**Configure LSE Drive Capability 25 */ 26 HAL_PWR_EnableBkUpAccess(); 27 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); 28 29 /**Initializes the CPU, AHB and APB busses clocks 30 */ 31 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE 32 |RCC_OSCILLATORTYPE_LSE; 33 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIG; 34 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 35 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 36 RCC_OscInitStruct.HSICalibrationValue = 16; 37 RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1; 38 39 /**PLL1 Config 40 */ 41 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 42 RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE; 43 RCC_OscInitStruct.PLL.PLLM = 3; 44 RCC_OscInitStruct.PLL.PLLN = 81; 45 RCC_OscInitStruct.PLL.PLLP = 1; 46 RCC_OscInitStruct.PLL.PLLQ = 1; 47 RCC_OscInitStruct.PLL.PLLR = 1; 48 RCC_OscInitStruct.PLL.PLLFRACV = 0x800; 49 RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL; 50 RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 51 RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 52 53 /**PLL2 Config 54 */ 55 RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; 56 RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE; 57 RCC_OscInitStruct.PLL2.PLLM = 3; 58 RCC_OscInitStruct.PLL2.PLLN = 66; 59 RCC_OscInitStruct.PLL2.PLLP = 2; 60 RCC_OscInitStruct.PLL2.PLLQ = 1; 61 RCC_OscInitStruct.PLL2.PLLR = 1; 62 RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400; 63 RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL; 64 RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 65 RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 66 67 /**PLL3 Config 68 */ 69 RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; 70 RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE; 71 RCC_OscInitStruct.PLL3.PLLM = 2; 72 RCC_OscInitStruct.PLL3.PLLN = 34; 73 RCC_OscInitStruct.PLL3.PLLP = 2; 74 RCC_OscInitStruct.PLL3.PLLQ = 17; 75 RCC_OscInitStruct.PLL3.PLLR = 37; 76 RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1; 77 RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04; 78 RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL; 79 RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 80 RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 81 82 /**PLL4 Config 83 */ 84 RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON; 85 RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE; 86 RCC_OscInitStruct.PLL4.PLLM = 4; 87 RCC_OscInitStruct.PLL4.PLLN = 99; 88 RCC_OscInitStruct.PLL4.PLLP = 6; 89 RCC_OscInitStruct.PLL4.PLLQ = 8; 90 RCC_OscInitStruct.PLL4.PLLR = 8; 91 RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0; 92 RCC_OscInitStruct.PLL4.PLLFRACV = 0; 93 RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER; 94 RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 95 RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 96 97 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 98 { 99 Error_Handler(); 100 } 101 /**RCC Clock Config 102 */ 103 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK 104 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 105 |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4 106 |RCC_CLOCKTYPE_PCLK5|RCC_CLOCKTYPE_MPU; 107 RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1; 108 RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2; 109 RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2; 110 RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1; 111 RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3; 112 RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1; 113 RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2; 114 RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4; 115 RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2; 116 RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2; 117 RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2; 118 119 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) 120 { 121 Error_Handler(); 122 } 123 124 /**Set the HSE division factor for RTC clock 125 */ 126 __HAL_RCC_RTC_HSEDIV(24); 127 } 128 129 130 /** 131 * @brief Peripherals Common Clock Configuration 132 * @retval None 133 */ PeriphCommonClock_Config(void)134void PeriphCommonClock_Config(void) { 135 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 136 137 /** Initializes the common periph clock 138 */ 139 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER; 140 PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE; 141 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { 142 Error_Handler(); 143 } 144 } 145 146 extern void rt_hw_systick_init(void); 147 extern int rt_hw_usart_init(void); rt_hw_board_init()148void rt_hw_board_init() 149 { 150 /* HAL_Init() function is called at the beginning of the program */ 151 HAL_Init(); 152 153 /* enable interrupt */ 154 __set_PRIMASK(0); 155 /* Configure the system clock */ 156 if (IS_ENGINEERING_BOOT_MODE()) { 157 /* Configure the system clock */ 158 SystemClock_Config(); 159 } 160 /* disable interrupt */ 161 __set_PRIMASK(1); 162 163 rt_hw_systick_init(); 164 165 /* Heap initialization */ 166 #if defined(RT_USING_HEAP) 167 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); 168 #endif 169 170 /* Pin driver initialization is open by default */ 171 #ifdef RT_USING_PIN 172 rt_hw_pin_init(); 173 #endif 174 175 /* USART driver initialization is open by default */ 176 #ifdef RT_USING_SERIAL 177 rt_hw_usart_init(); 178 #endif 179 180 /* Set the shell console output device */ 181 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) 182 rt_console_set_device(RT_CONSOLE_DEVICE_NAME); 183 #endif 184 185 /* Board underlying hardware initialization */ 186 #ifdef RT_USING_COMPONENTS_INIT 187 rt_components_board_init(); 188 #endif 189 } 190