1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-01-05 linyiyang first version
9 * 2024-05-28 WKjay add this file to stm32f103-100ask-pro
10 */
11
12 #include <rtthread.h>
13 #include <rtdevice.h>
14 #include <board.h>
15
16 #ifdef BSP_USING_EXT_SRAM
17 #include <sram_port.h>
18
19 #define DRV_DEBUG
20 #define LOG_TAG "drv.ext_sram"
21 #include <drv_log.h>
22
23 static SRAM_HandleTypeDef hsram1;
24 #ifdef RT_USING_MEMHEAP_AS_HEAP
25 static struct rt_memheap system_heap;
26 #endif
27
external_sram_init(void)28 static int external_sram_init(void)
29 {
30 int result = RT_EOK;
31
32 FSMC_NORSRAM_TimingTypeDef Timing = {0};
33
34 /** Perform the SRAM1 memory initialization sequence
35 */
36 hsram1.Instance = FSMC_NORSRAM_DEVICE;
37 hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
38
39 /* hsram1.Init */
40 hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
41 hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
42 hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
43 #if EXTERNAL_SRAM_DATA_WIDTH == 8
44 hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
45 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
46 hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
47 #else
48 hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_32;
49 #endif
50 hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
51 hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
52 hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
53 hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
54 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
55 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
56 hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
57 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
58 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
59
60 /* Timing */
61 Timing.AddressSetupTime = 0;
62 Timing.AddressHoldTime = 15;
63 Timing.DataSetupTime = 3;
64 Timing.BusTurnAroundDuration = 0;
65 Timing.CLKDivision = 16;
66 Timing.DataLatency = 17;
67 Timing.AccessMode = FSMC_ACCESS_MODE_A;
68 /* ExtTiming */
69
70 /* Initialize the SRAM controller */
71 if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
72 {
73 LOG_E("External SRAM init failed!");
74 result = -RT_ERROR;
75 }
76 else
77 {
78 LOG_D("External sram init success, mapped at 0x%X, size is %d bytes, data width is %d", EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE, EXTERNAL_SRAM_DATA_WIDTH);
79 #ifdef RT_USING_MEMHEAP_AS_HEAP
80 /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
81 rt_memheap_init(&system_heap, "ext_sram", (void *)EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE);
82 #endif
83 }
84
85 /** Disconnect NADV
86 */
87
88 __HAL_AFIO_FSMCNADV_DISCONNECTED();
89
90 return result;
91 }
92 INIT_BOARD_EXPORT(external_sram_init);
93
94 #ifdef DRV_DEBUG
95 #ifdef FINSH_USING_MSH
external_sram_test(void)96 int external_sram_test(void)
97 {
98 int i = 0;
99 uint32_t start_time = 0, time_cast = 0;
100 #if EXTERNAL_SRAM_DATA_WIDTH == 8
101 char data_width = 1;
102 uint8_t data = 0;
103 uint8_t *ptr = (uint8_t *)EXTERNAL_SRAM_BANK_ADDR;
104 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
105 char data_width = 2;
106 uint16_t data = 0;
107 uint16_t *ptr = (uint16_t *)EXTERNAL_SRAM_BANK_ADDR;
108 #else
109 char data_width = 4;
110 uint32_t data = 0;
111 uint32_t *ptr = (uint32_t *)EXTERNAL_SRAM_BANK_ADDR;
112 #endif
113
114 /* write data */
115 LOG_D("Writing the %ld bytes data, waiting....", EXTERNAL_SRAM_SIZE);
116 start_time = rt_tick_get();
117 for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
118 {
119 #if EXTERNAL_SRAM_DATA_WIDTH == 8
120 ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
121 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
122 ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
123 #else
124 ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
125 #endif
126 }
127 time_cast = rt_tick_get() - start_time;
128 LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
129 time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
130
131 /* read data */
132 LOG_D("start Reading and verifying data, waiting....");
133 for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
134 {
135 #if EXTERNAL_SRAM_DATA_WIDTH == 8
136 data = ((__IO uint8_t *)ptr)[i];
137 if (data != 0x55)
138 {
139 LOG_E("External SRAM test failed!");
140 break;
141 }
142 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
143 data = ((__IO uint16_t *)ptr)[i];
144 if (data != 0x5555)
145 {
146 LOG_E("External SRAM test failed!");
147 break;
148 }
149 #else
150 data = ((__IO uint32_t *)ptr)[i];
151 if (data != 0x55555555)
152 {
153 LOG_E("External SRAM test failed!");
154 break;
155 }
156 #endif
157 }
158
159 if (i >= EXTERNAL_SRAM_SIZE / data_width)
160 {
161 LOG_D("External SRAM test success!");
162 }
163
164 return RT_EOK;
165 }
166 MSH_CMD_EXPORT(external_sram_test, sram test);
167 #endif /* FINSH_USING_MSH */
168 #endif /* DRV_DEBUG */
169 #endif /* BSP_USING_EXT_SRAM */
170