1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 balanceTWK first version 9 */ 10 11 #include <board.h> 12 #include <drv_common.h> 13 SystemClock_Config(void)14void SystemClock_Config(void) 15 { 16 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 17 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 18 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 19 20 /**Initializes the CPU, AHB and APB busses clocks 21 */ 22 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE 23 |RCC_OSCILLATORTYPE_LSE; 24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 25 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 26 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 27 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 29 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 30 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 31 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 32 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 33 { 34 Error_Handler(); 35 } 36 /**Initializes the CPU, AHB and APB busses clocks 37 */ 38 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 39 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 40 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 41 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 42 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 43 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 44 45 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 46 { 47 Error_Handler(); 48 } 49 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 50 PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 51 PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 52 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 53 { 54 Error_Handler(); 55 } 56 } 57