1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-01-05 linyiyang first version
9 */
10
11 #include <rtthread.h>
12 #include <rtdevice.h>
13 #include <board.h>
14
15 #ifdef BSP_USING_EXT_SRAM
16 #include <sram_port.h>
17
18 #define DRV_DEBUG
19 #define LOG_TAG "drv.ext_sram"
20 #include <drv_log.h>
21
22 static SRAM_HandleTypeDef hsram1;
23 #ifdef RT_USING_MEMHEAP_AS_HEAP
24 static struct rt_memheap system_heap;
25 #endif
26
external_sram_init(void)27 static int external_sram_init(void)
28 {
29 int result = RT_EOK;
30
31 FSMC_NORSRAM_TimingTypeDef Timing = {0};
32
33 /** Perform the SRAM1 memory initialization sequence
34 */
35 hsram1.Instance = FSMC_NORSRAM_DEVICE;
36 hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
37
38 /* hsram1.Init */
39 hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
40 hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
41 hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
42 #if EXTERNAL_SRAM_DATA_WIDTH == 8
43 hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
44 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
45 hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
46 #else
47 hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_32;
48 #endif
49 hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
50 hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
51 hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
52 hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
53 hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
54 hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
55 hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
56 hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
57 hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
58
59 /* Timing */
60 Timing.AddressSetupTime = 0;
61 Timing.AddressHoldTime = 15;
62 Timing.DataSetupTime = 3;
63 Timing.BusTurnAroundDuration = 0;
64 Timing.CLKDivision = 16;
65 Timing.DataLatency = 17;
66 Timing.AccessMode = FSMC_ACCESS_MODE_A;
67 /* ExtTiming */
68
69 /* Initialize the SRAM controller */
70 if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
71 {
72 LOG_E("External SRAM init failed!");
73 result = -RT_ERROR;
74 }
75 else
76 {
77 LOG_D("External sram init success, mapped at 0x%X, size is %d bytes, data width is %d", EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE, EXTERNAL_SRAM_DATA_WIDTH);
78 #ifdef RT_USING_MEMHEAP_AS_HEAP
79 /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
80 rt_memheap_init(&system_heap, "ext_sram", (void *)EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE);
81 #endif
82 }
83
84 /** Disconnect NADV
85 */
86
87 __HAL_AFIO_FSMCNADV_DISCONNECTED();
88
89 return result;
90 }
91 INIT_BOARD_EXPORT(external_sram_init);
92
93 #ifdef DRV_DEBUG
94 #ifdef FINSH_USING_MSH
external_sram_test(void)95 int external_sram_test(void)
96 {
97 int i = 0;
98 uint32_t start_time = 0, time_cast = 0;
99 #if EXTERNAL_SRAM_DATA_WIDTH == 8
100 char data_width = 1;
101 uint8_t data = 0;
102 uint8_t *ptr = (uint8_t *)EXTERNAL_SRAM_BANK_ADDR;
103 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
104 char data_width = 2;
105 uint16_t data = 0;
106 uint16_t *ptr = (uint16_t *)EXTERNAL_SRAM_BANK_ADDR;
107 #else
108 char data_width = 4;
109 uint32_t data = 0;
110 uint32_t *ptr = (uint32_t *)EXTERNAL_SRAM_BANK_ADDR;
111 #endif
112
113 /* write data */
114 LOG_D("Writing the %ld bytes data, waiting....", EXTERNAL_SRAM_SIZE);
115 start_time = rt_tick_get();
116 for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
117 {
118 #if EXTERNAL_SRAM_DATA_WIDTH == 8
119 ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
120 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
121 ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
122 #else
123 ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
124 #endif
125 }
126 time_cast = rt_tick_get() - start_time;
127 LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
128 time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
129
130 /* read data */
131 LOG_D("start Reading and verifying data, waiting....");
132 for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
133 {
134 #if EXTERNAL_SRAM_DATA_WIDTH == 8
135 data = ((__IO uint8_t *)ptr)[i];
136 if (data != 0x55)
137 {
138 LOG_E("External SRAM test failed!");
139 break;
140 }
141 #elif EXTERNAL_SRAM_DATA_WIDTH == 16
142 data = ((__IO uint16_t *)ptr)[i];
143 if (data != 0x5555)
144 {
145 LOG_E("External SRAM test failed!");
146 break;
147 }
148 #else
149 data = ((__IO uint32_t *)ptr)[i];
150 if (data != 0x55555555)
151 {
152 LOG_E("External SRAM test failed!");
153 break;
154 }
155 #endif
156 }
157
158 if (i >= EXTERNAL_SRAM_SIZE / data_width)
159 {
160 LOG_D("External SRAM test success!");
161 }
162
163 return RT_EOK;
164 }
165 MSH_CMD_EXPORT(external_sram_test, sram test);
166 #endif /* FINSH_USING_MSH */
167 #endif /* DRV_DEBUG */
168 #endif /* BSP_USING_EXT_SRAM */
169