1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 balanceTWK first version 9 */ 10 11 #include <board.h> 12 #include <drv_common.h> 13 14 /** 15 * @brief System Clock Configuration 16 * @retval None 17 */ SystemClock_Config(void)18void SystemClock_Config(void) 19 { 20 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 21 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 22 23 /** Initializes the CPU, AHB and APB busses clocks 24 */ 25 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 26 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 27 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 29 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; 30 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; 31 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 32 { 33 Error_Handler(); 34 } 35 /** Initializes the CPU, AHB and APB busses clocks 36 */ 37 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 38 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 39 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 40 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 41 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 42 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 43 44 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 45 { 46 Error_Handler(); 47 } 48 } 49