1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Date Author Notes 7 * 2019-07-31 Zero-Free first implementation 8 */ 9 10 #ifndef __DRV_ES8388_H__ 11 #define __DRV_ES8388_H__ 12 13 /* ES8388 register space */ 14 #define ES8388_CONTROL1 0x00 15 #define ES8388_CONTROL2 0x01 16 #define ES8388_CHIPPOWER 0x02 17 #define ES8388_ADCPOWER 0x03 18 #define ES8388_DACPOWER 0x04 19 #define ES8388_CHIPLOPOW1 0x05 20 #define ES8388_CHIPLOPOW2 0x06 21 #define ES8388_ANAVOLMANAG 0x07 22 #define ES8388_MASTERMODE 0x08 23 #define ES8388_ADCCONTROL1 0x09 24 #define ES8388_ADCCONTROL2 0x0a 25 #define ES8388_ADCCONTROL3 0x0b 26 #define ES8388_ADCCONTROL4 0x0c 27 #define ES8388_ADCCONTROL5 0x0d 28 #define ES8388_ADCCONTROL6 0x0e 29 #define ES8388_ADCCONTROL7 0x0f 30 #define ES8388_ADCCONTROL8 0x10 31 #define ES8388_ADCCONTROL9 0x11 32 #define ES8388_ADCCONTROL10 0x12 33 #define ES8388_ADCCONTROL11 0x13 34 #define ES8388_ADCCONTROL12 0x14 35 #define ES8388_ADCCONTROL13 0x15 36 #define ES8388_ADCCONTROL14 0x16 37 38 #define ES8388_DACCONTROL1 0x17 39 #define ES8388_DACCONTROL2 0x18 40 #define ES8388_DACCONTROL3 0x19 41 #define ES8388_DACCONTROL4 0x1a 42 #define ES8388_DACCONTROL5 0x1b 43 #define ES8388_DACCONTROL6 0x1c 44 #define ES8388_DACCONTROL7 0x1d 45 #define ES8388_DACCONTROL8 0x1e 46 #define ES8388_DACCONTROL9 0x1f 47 #define ES8388_DACCONTROL10 0x20 48 #define ES8388_DACCONTROL11 0x21 49 #define ES8388_DACCONTROL12 0x22 50 #define ES8388_DACCONTROL13 0x23 51 #define ES8388_DACCONTROL14 0x24 52 #define ES8388_DACCONTROL15 0x25 53 #define ES8388_DACCONTROL16 0x26 54 #define ES8388_DACCONTROL17 0x27 55 #define ES8388_DACCONTROL18 0x28 56 #define ES8388_DACCONTROL19 0x29 57 #define ES8388_DACCONTROL20 0x2a 58 #define ES8388_DACCONTROL21 0x2b 59 #define ES8388_DACCONTROL22 0x2c 60 #define ES8388_DACCONTROL23 0x2d 61 #define ES8388_DACCONTROL24 0x2e 62 #define ES8388_DACCONTROL25 0x2f 63 #define ES8388_DACCONTROL26 0x30 64 #define ES8388_DACCONTROL27 0x31 65 #define ES8388_DACCONTROL28 0x32 66 #define ES8388_DACCONTROL29 0x33 67 #define ES8388_DACCONTROL30 0x34 68 69 enum es8388_mode 70 { 71 ES_MODE_NONE = 0x00, 72 ES_MODE_DAC = 0x01, 73 ES_MODE_ADC = 0x02, 74 ES_MODE_DAC_ADC = 0x03, 75 ES_MODE_LINE = 0x04, 76 ES_MODE_MAX = 0x06, 77 }; 78 79 enum es8388_format 80 { 81 ES_FMT_NORMAL = 0, 82 ES_FMT_LEFT = 1, 83 ES_FMT_RIGHT = 2, 84 ES_FMT_DSP = 3, 85 }; 86 87 rt_err_t es8388_init(const char *i2c_name, rt_uint16_t pin); 88 rt_err_t es8388_start(enum es8388_mode mode); 89 rt_err_t es8388_stop(enum es8388_mode mode); 90 rt_err_t es8388_fmt_set(enum es8388_mode mode, enum es8388_format fmt); 91 void es8388_volume_set(rt_uint8_t volume); 92 rt_uint8_t es8388_volume_get(void); 93 void es8388_pa_power(rt_bool_t enable); 94 95 #endif 96