1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-08-11 RT-Thread the first version 9 */ 10 #ifndef __ILI9341_H 11 #define __ILI9341_H 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 18 /** 19 * @brief ILI9341 chip IDs 20 */ 21 #define ILI9341_ID 0x9341 22 23 /** 24 * @brief ILI9341 Registers 25 */ 26 27 /* Level 1 Commands */ 28 #define LCD_SWRESET 0x01 /* Software Reset */ 29 #define LCD_READ_DISPLAY_ID 0x04 /* Read display identification information */ 30 #define LCD_RDDST 0x09 /* Read Display Status */ 31 #define LCD_RDDPM 0x0A /* Read Display Power Mode */ 32 #define LCD_RDDMADCTL 0x0B /* Read Display MADCTL */ 33 #define LCD_RDDCOLMOD 0x0C /* Read Display Pixel Format */ 34 #define LCD_RDDIM 0x0D /* Read Display Image Format */ 35 #define LCD_RDDSM 0x0E /* Read Display Signal Mode */ 36 #define LCD_RDDSDR 0x0F /* Read Display Self-Diagnostic Result */ 37 #define LCD_SPLIN 0x10 /* Enter Sleep Mode */ 38 #define LCD_SLEEP_OUT 0x11 /* Sleep out register */ 39 #define LCD_PTLON 0x12 /* Partial Mode ON */ 40 #define LCD_NORMAL_MODE_ON 0x13 /* Normal Display Mode ON */ 41 #define LCD_DINVOFF 0x20 /* Display Inversion OFF */ 42 #define LCD_DINVON 0x21 /* Display Inversion ON */ 43 #define LCD_GAMMA 0x26 /* Gamma register */ 44 #define LCD_DISPLAY_OFF 0x28 /* Display off register */ 45 #define LCD_DISPLAY_ON 0x29 /* Display on register */ 46 #define LCD_COLUMN_ADDR 0x2A /* Colomn address register */ 47 #define LCD_PAGE_ADDR 0x2B /* Page address register */ 48 #define LCD_GRAM 0x2C /* GRAM register */ 49 #define LCD_RGBSET 0x2D /* Color SET */ 50 #define LCD_RAMRD 0x2E /* Memory Read */ 51 #define LCD_PLTAR 0x30 /* Partial Area */ 52 #define LCD_VSCRDEF 0x33 /* Vertical Scrolling Definition */ 53 #define LCD_TEOFF 0x34 /* Tearing Effect Line OFF */ 54 #define LCD_TEON 0x35 /* Tearing Effect Line ON */ 55 #define LCD_MAC 0x36 /* Memory Access Control register*/ 56 #define LCD_VSCRSADD 0x37 /* Vertical Scrolling Start Address */ 57 #define LCD_IDMOFF 0x38 /* Idle Mode OFF */ 58 #define LCD_IDMON 0x39 /* Idle Mode ON */ 59 #define LCD_PIXEL_FORMAT 0x3A /* Pixel Format register */ 60 #define LCD_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */ 61 #define LCD_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */ 62 #define LCD_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */ 63 #define LCD_GET_SCANLINE 0x45 /* Get Scanline */ 64 #define LCD_WDB 0x51 /* Write Brightness Display register */ 65 #define LCD_RDDISBV 0x52 /* Read Display Brightness */ 66 #define LCD_WCD 0x53 /* Write Control Display register*/ 67 #define LCD_RDCTRLD 0x54 /* Read CTRL Display */ 68 #define LCD_WRCABC 0x55 /* Write Content Adaptive Brightness Control */ 69 #define LCD_RDCABC 0x56 /* Read Content Adaptive Brightness Control */ 70 #define LCD_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */ 71 #define LCD_READ_CABC 0x5F /* Read CABC Minimum Brightness */ 72 #define LCD_READ_ID1 0xDA /* Read ID1 */ 73 #define LCD_READ_ID2 0xDB /* Read ID2 */ 74 #define LCD_READ_ID3 0xDC /* Read ID3 */ 75 76 /* Level 2 Commands */ 77 #define LCD_RGB_INTERFACE 0xB0 /* RGB Interface Signal Control */ 78 #define LCD_FRMCTR1 0xB1 /* Frame Rate Control (In Normal Mode) */ 79 #define LCD_FRMCTR2 0xB2 /* Frame Rate Control (In Idle Mode) */ 80 #define LCD_FRMCTR3 0xB3 /* Frame Rate Control (In Partial Mode) */ 81 #define LCD_INVTR 0xB4 /* Display Inversion Control */ 82 #define LCD_BPC 0xB5 /* Blanking Porch Control register */ 83 #define LCD_DFC 0xB6 /* Display Function Control register */ 84 #define LCD_ETMOD 0xB7 /* Entry Mode Set */ 85 #define LCD_BACKLIGHT1 0xB8 /* Backlight Control 1 */ 86 #define LCD_BACKLIGHT2 0xB9 /* Backlight Control 2 */ 87 #define LCD_BACKLIGHT3 0xBA /* Backlight Control 3 */ 88 #define LCD_BACKLIGHT4 0xBB /* Backlight Control 4 */ 89 #define LCD_BACKLIGHT5 0xBC /* Backlight Control 5 */ 90 #define LCD_BACKLIGHT7 0xBE /* Backlight Control 7 */ 91 #define LCD_BACKLIGHT8 0xBF /* Backlight Control 8 */ 92 #define LCD_POWER1 0xC0 /* Power Control 1 register */ 93 #define LCD_POWER2 0xC1 /* Power Control 2 register */ 94 #define LCD_VCOM1 0xC5 /* VCOM Control 1 register */ 95 #define LCD_VCOM2 0xC7 /* VCOM Control 2 register */ 96 #define LCD_NVMWR 0xD0 /* NV Memory Write */ 97 #define LCD_NVMPKEY 0xD1 /* NV Memory Protection Key */ 98 #define LCD_RDNVM 0xD2 /* NV Memory Status Read */ 99 #define LCD_READ_ID4 0xD3 /* Read ID4 */ 100 #define LCD_PGAMMA 0xE0 /* Positive Gamma Correction register */ 101 #define LCD_NGAMMA 0xE1 /* Negative Gamma Correction register */ 102 #define LCD_DGAMCTRL1 0xE2 /* Digital Gamma Control 1 */ 103 #define LCD_DGAMCTRL2 0xE3 /* Digital Gamma Control 2 */ 104 #define LCD_INTERFACE 0xF6 /* Interface control register */ 105 106 /* Extend register commands */ 107 #define LCD_POWERA 0xCB /* Power control A register */ 108 #define LCD_POWERB 0xCF /* Power control B register */ 109 #define LCD_DTCA 0xE8 /* Driver timing control A */ 110 #define LCD_DTCB 0xEA /* Driver timing control B */ 111 #define LCD_POWER_SEQ 0xED /* Power on sequence register */ 112 #define LCD_3GAMMA_EN 0xF2 /* 3 Gamma enable register */ 113 #define LCD_PRC 0xF7 /* Pump ratio control register */ 114 115 /* Size of read registers */ 116 #define LCD_READ_ID4_SIZE 3 /* Size of Read ID4 */ 117 118 119 /** @defgroup ILI9341_Exported_Functions 120 * @{ 121 */ 122 int ili9341_hw_init(void); 123 124 125 #ifdef __cplusplus 126 } 127 #endif 128 129 #endif /* __ILI9341_H */ 130 131 132