1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-08-08 bernard The first version for STM32F429 DISCO 9 */ 10 11 #ifndef __SDRAM_PORT_H__ 12 #define __SDRAM_PORT_H__ 13 14 /* parameters for sdram peripheral */ 15 /* Bank1 or Bank2 */ 16 #define SDRAM_TARGET_BANK 2 17 /* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */ 18 #define SDRAM_BANK_ADDR ((uint32_t)0XD0000000) 19 /* data width: 8, 16, 32 */ 20 #define SDRAM_DATA_WIDTH 16 21 /* column bit numbers: 8, 9, 10, 11 */ 22 #define SDRAM_COLUMN_BITS 8 23 /* row bit numbers: 11, 12, 13 */ 24 #define SDRAM_ROW_BITS 12 25 /* cas latency clock number: 1, 2, 3 */ 26 #define SDRAM_CAS_LATENCY 3 27 /* read pipe delay: 0, 1, 2 */ 28 #define SDRAM_RPIPE_DELAY 1 29 /* clock divid: 2, 3 */ 30 #define SDCLOCK_PERIOD 2 31 /* refresh rate counter */ 32 #define SDRAM_REFRESH_COUNT ((uint32_t)0x056A) 33 #define SDRAM_SIZE ((uint32_t)0x800000) 34 35 /* Timing configuration for IS42S16400J */ 36 /* 90 MHz of SD clock frequency (180MHz/2) */ 37 /* TMRD: 2 Clock cycles */ 38 #define LOADTOACTIVEDELAY 2 39 /* TXSR: 7x11.90ns */ 40 #define EXITSELFREFRESHDELAY 7 41 /* TRAS: 4x11.90ns */ 42 #define SELFREFRESHTIME 4 43 /* TRC: 7x11.90ns */ 44 #define ROWCYCLEDELAY 7 45 /* TWR: 2 Clock cycles */ 46 #define WRITERECOVERYTIME 2 47 /* TRP: 2x11.90ns */ 48 #define RPDELAY 2 49 /* TRCD: 2x11.90ns */ 50 #define RCDDELAY 2 51 52 /* memory mode register */ 53 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) 54 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) 55 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) 56 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) 57 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) 58 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) 59 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) 60 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) 61 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 62 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 63 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) 64 65 #endif 66