1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 SummerGift first version 9 * 2019-01-08 AndeyQi add stm32f446-st-nucleo bsp 10 */ 11 12 #include <board.h> 13 #include <drv_common.h> 14 SystemClock_Config(void)15void SystemClock_Config(void) 16 { 17 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 18 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 19 20 /**Configure the main internal regulator output voltage 21 */ 22 __HAL_RCC_PWR_CLK_ENABLE(); 23 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 24 /**Initializes the CPU, AHB and APB busses clocks 25 */ 26 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 27 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 29 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 30 RCC_OscInitStruct.PLL.PLLM = 4; 31 RCC_OscInitStruct.PLL.PLLN = 180; 32 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 33 RCC_OscInitStruct.PLL.PLLQ = 2; 34 RCC_OscInitStruct.PLL.PLLR = 2; 35 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 36 { 37 Error_Handler(); 38 } 39 /**Activate the Over-Drive mode 40 */ 41 if (HAL_PWREx_EnableOverDrive() != HAL_OK) 42 { 43 Error_Handler(); 44 } 45 /**Initializes the CPU, AHB and APB busses clocks 46 */ 47 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 48 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 49 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 50 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 51 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 52 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 53 54 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 55 { 56 Error_Handler(); 57 } 58 } 59