1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-01-06 jinsheng first version 9 */ 10 11 #include "board.h" 12 13 /** 14 * @brief System Clock Configuration 15 * @retval None 16 */ SystemClock_Config(void)17void SystemClock_Config(void) 18 { 19 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 20 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 21 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 22 23 /**Configure LSE Drive Capability 24 */ 25 HAL_PWR_EnableBkUpAccess(); 26 /**Configure the main internal regulator output voltage 27 */ 28 __HAL_RCC_PWR_CLK_ENABLE(); 29 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 30 /**Initializes the CPU, AHB and APB busses clocks 31 */ 32 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; 33 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 34 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 35 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 36 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 37 RCC_OscInitStruct.PLL.PLLM = 25; 38 RCC_OscInitStruct.PLL.PLLN = 432; 39 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 40 RCC_OscInitStruct.PLL.PLLQ = 9; 41 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 42 { 43 Error_Handler(); 44 } 45 /**Activate the Over-Drive mode 46 */ 47 if (HAL_PWREx_EnableOverDrive() != HAL_OK) 48 { 49 Error_Handler(); 50 } 51 /**Initializes the CPU, AHB and APB busses clocks 52 */ 53 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 54 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 55 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 56 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 57 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 58 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 59 60 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) 61 { 62 Error_Handler(); 63 } 64 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART1 65 |RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; 66 PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; 67 PeriphClkInitStruct.PLLSAI.PLLSAIR = 5; 68 PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; 69 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; 70 PeriphClkInitStruct.PLLSAIDivQ = 1; 71 PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_4; 72 PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 73 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; 74 PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; 75 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 76 { 77 Error_Handler(); 78 } 79 } 80