1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 SummerGift first version 9 */ 10 11 #include "board.h" 12 SystemClock_Config(void)13void SystemClock_Config(void) 14 { 15 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 16 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 17 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 18 19 /** Configure LSE Drive Capability 20 */ 21 HAL_PWR_EnableBkUpAccess(); 22 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); 23 /** Configure the main internal regulator output voltage 24 */ 25 __HAL_RCC_PWR_CLK_ENABLE(); 26 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 27 /** Initializes the CPU, AHB and APB busses clocks 28 */ 29 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE 30 |RCC_OSCILLATORTYPE_LSE; 31 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 32 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 33 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 35 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 36 RCC_OscInitStruct.PLL.PLLM = 25; 37 RCC_OscInitStruct.PLL.PLLN = 432; 38 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 39 RCC_OscInitStruct.PLL.PLLQ = 9; 40 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 41 { 42 Error_Handler(); 43 } 44 /** Activate the Over-Drive mode 45 */ 46 if (HAL_PWREx_EnableOverDrive() != HAL_OK) 47 { 48 Error_Handler(); 49 } 50 /** Initializes the CPU, AHB and APB busses clocks 51 */ 52 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 53 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 54 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 55 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 56 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 57 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 58 59 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) 60 { 61 Error_Handler(); 62 } 63 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_RTC 64 |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2 65 |RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; 66 PeriphClkInitStruct.PLLSAI.PLLSAIN = 288; 67 PeriphClkInitStruct.PLLSAI.PLLSAIR = 4; 68 PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; 69 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; 70 PeriphClkInitStruct.PLLSAIDivQ = 1; 71 PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8; 72 PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 73 PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 74 PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; 75 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; 76 PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; 77 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 78 { 79 Error_Handler(); 80 } 81 } 82