1 /**
2 ******************************************************************************
3 * @file system_stm32g4xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32g4xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the HSI (16 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | HSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 16000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 16000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_M | 1
41 *-----------------------------------------------------------------------------
42 * PLL_N | 16
43 *-----------------------------------------------------------------------------
44 * PLL_P | 7
45 *-----------------------------------------------------------------------------
46 * PLL_Q | 2
47 *-----------------------------------------------------------------------------
48 * PLL_R | 2
49 *-----------------------------------------------------------------------------
50 * Require 48MHz for RNG | Disabled
51 *-----------------------------------------------------------------------------
52 *=============================================================================
53 ******************************************************************************
54 * @attention
55 *
56 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
57 * All rights reserved.</center></h2>
58 *
59 * This software component is licensed by ST under BSD 3-Clause license,
60 * the "License"; You may not use this file except in compliance with the
61 * License. You may obtain a copy of the License at:
62 * opensource.org/licenses/BSD-3-Clause
63 *
64 ******************************************************************************
65 */
66
67 /** @addtogroup CMSIS
68 * @{
69 */
70
71 /** @addtogroup stm32g4xx_system
72 * @{
73 */
74
75 /** @addtogroup STM32G4xx_System_Private_Includes
76 * @{
77 */
78
79 #include "stm32g4xx.h"
80
81 #if !defined (HSE_VALUE)
82 #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
83 #endif /* HSE_VALUE */
84
85 #if !defined (HSI_VALUE)
86 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
87 #endif /* HSI_VALUE */
88
89 /**
90 * @}
91 */
92
93 /** @addtogroup STM32G4xx_System_Private_TypesDefinitions
94 * @{
95 */
96
97 /**
98 * @}
99 */
100
101 /** @addtogroup STM32G4xx_System_Private_Defines
102 * @{
103 */
104
105 /************************* Miscellaneous Configuration ************************/
106 /*!< Uncomment the following line if you need to relocate your vector Table in
107 Internal SRAM. */
108 /* #define VECT_TAB_SRAM */
109 #define VECT_TAB_OFFSET 0x00UL /*!< Vector Table base offset field.
110 This value must be a multiple of 0x200. */
111 /******************************************************************************/
112 /**
113 * @}
114 */
115
116 /** @addtogroup STM32G4xx_System_Private_Macros
117 * @{
118 */
119
120 /**
121 * @}
122 */
123
124 /** @addtogroup STM32G4xx_System_Private_Variables
125 * @{
126 */
127 /* The SystemCoreClock variable is updated in three ways:
128 1) by calling CMSIS function SystemCoreClockUpdate()
129 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
130 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
131 Note: If you use this function to configure the system clock; then there
132 is no need to call the 2 first functions listed above, since SystemCoreClock
133 variable is updated automatically.
134 */
135 uint32_t SystemCoreClock = HSI_VALUE;
136
137 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
138 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
139
140 /**
141 * @}
142 */
143
144 /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
145 * @{
146 */
147
148 /**
149 * @}
150 */
151
152 /** @addtogroup STM32G4xx_System_Private_Functions
153 * @{
154 */
155
156 /**
157 * @brief Setup the microcontroller system.
158 * @param None
159 * @retval None
160 */
161
SystemInit(void)162 void SystemInit(void)
163 {
164 /* FPU settings ------------------------------------------------------------*/
165 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
166 SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
167 #endif
168
169 /* Configure the Vector Table location add offset address ------------------*/
170 #ifdef VECT_TAB_SRAM
171 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
172 #else
173 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
174 #endif
175 }
176
177 /**
178 * @brief Update SystemCoreClock variable according to Clock Register Values.
179 * The SystemCoreClock variable contains the core clock (HCLK), it can
180 * be used by the user application to setup the SysTick timer or configure
181 * other parameters.
182 *
183 * @note Each time the core clock (HCLK) changes, this function must be called
184 * to update SystemCoreClock variable value. Otherwise, any configuration
185 * based on this variable will be incorrect.
186 *
187 * @note - The system frequency computed by this function is not the real
188 * frequency in the chip. It is calculated based on the predefined
189 * constant and the selected clock source:
190 *
191 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
192 *
193 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
194 *
195 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
196 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
197 *
198 * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
199 * 16 MHz) but the real value may vary depending on the variations
200 * in voltage and temperature.
201 *
202 * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
203 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
204 * frequency of the crystal used. Otherwise, this function may
205 * have wrong result.
206 *
207 * - The result of this function could be not correct when using fractional
208 * value for HSE crystal.
209 *
210 * @param None
211 * @retval None
212 */
SystemCoreClockUpdate(void)213 void SystemCoreClockUpdate(void)
214 {
215 uint32_t tmp, pllvco, pllr, pllsource, pllm;
216
217 /* Get SYSCLK source -------------------------------------------------------*/
218 switch (RCC->CFGR & RCC_CFGR_SWS)
219 {
220 case 0x04: /* HSI used as system clock source */
221 SystemCoreClock = HSI_VALUE;
222 break;
223
224 case 0x08: /* HSE used as system clock source */
225 SystemCoreClock = HSE_VALUE;
226 break;
227
228 case 0x0C: /* PLL used as system clock source */
229 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
230 SYSCLK = PLL_VCO / PLLR
231 */
232 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
233 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
234 if (pllsource == 0x02UL) /* HSI used as PLL clock source */
235 {
236 pllvco = (HSI_VALUE / pllm);
237 }
238 else /* HSE used as PLL clock source */
239 {
240 pllvco = (HSE_VALUE / pllm);
241 }
242 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
243 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
244 SystemCoreClock = pllvco/pllr;
245 break;
246
247 default:
248 break;
249 }
250 /* Compute HCLK clock frequency --------------------------------------------*/
251 /* Get HCLK prescaler */
252 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
253 /* HCLK clock frequency */
254 SystemCoreClock >>= tmp;
255 }
256
257
258 /**
259 * @}
260 */
261
262 /**
263 * @}
264 */
265
266 /**
267 * @}
268 */
269
270 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
271
272