README.md
1# STM32H723-Nucleo BSP Introduction
2
3[中文](README_zh.md)
4
5### Description
6
7STM32H723xE/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating-point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H723xE/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
8
9STM32H723xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte of flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI, 128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multilayer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).
10
11The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC coprocessor for trigonometric functions and FMAC unit for filter functions). All the devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low-power comparators, a low-power RTC, four general-purpose 32-bit timers, 12 general-purpose 16-bit timers including two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.
12
13### All features
14
15- Includes ST state-of-the-art patented technology
16- Core
17 - 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
18- Memories
19 - Up to 1 Mbyte of embedded flash memory with ECC
20 - SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical real-time data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)
21 - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
22 - 2 x Octo-SPI interface with XiP
23 - 2 x SD/SDIO/MMC interface
24 - Bootloader
25- Graphics
26 - Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load
27 - LCD-TFT controller supporting up to XGA resolution
28- Clock, reset and supply management
29 - 1.62 V to 3.6 V application supply and I/O
30 - POR, PDR, PVD and BOR
31 - Dedicated USB power
32 - Embedded LDO regulator
33 - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
34 - External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
35- Low power
36 - Sleep, Stop and Standby modes
37 - VBAT supply for RTC, 32×32-bit backup registers
38- Analog
39 - 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to 18 channels and 7.2 MSPS in double-interleaved mode
40 - 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels
41 - 2 x comparators
42 - 2 x operational amplifier GBW = 8 MHz
43 - 2× 12-bit D/A converters
44- Digital filters for sigma delta modulator (DFSDM)
45 - 8 channels/4 filters
46- 4 DMA controllers to offload the CPU
47 - 1 × MDMA with linked list support
48 - 2 × dual-port DMAs with FIFO
49 - 1 × basic DMA with request router capabilities
50- 24 timers
51 - Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
52 - 2x watchdogs, 1x SysTick timer
53- Debug mode
54 - SWD and JTAG interfaces
55 - 2-Kbyte embedded trace buffer
56
57- Up to 114 I/O ports with interrupt capability
58- Up to 35 communication interfaces
59 - Up to 5 × I2C FM+ interfaces (SMBus/PMBus™)
60 - Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART
61 - Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode)
62 - 2x SAI (serial audio interface)
63 - 1× FD/TT-CAN and 2x FD-CAN
64 - 8- to 14-bit camera interface
65 - 16-bit parallel slave synchronous interface
66 - SPDIF-IN interface
67 - HDMI-CEC
68 - Ethernet MAC interface with DMA controller
69 - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY
70 - SWPMI single-wire protocol master I/F
71 - MDIO slave interface
72- Mathematical acceleration
73 - CORDIC for trigonometric functions acceleration
74 - FMAC: Filter mathematical accelerator
75- Digital temperature sensor
76- True random number generator
77- CRC calculation unit
78- RTC with subsecond accuracy and hardware calendar
79- ROP, PC-ROP, tamper detection
80- 96-bit unique ID
81- All packages are ECOPACK2 compliant
82
83## Read more
84
85| Documents | Description |
86| :----------------------------------------------------------: | :----------------------------------------------------------: |
87| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) |
88| [STM32H723ZG ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html#documentation) | STM32H723ZG datasheet and other resources |
89
90## Maintained By
91
92[hywing](https://github.com/hywing)
