1 /* 2 * Copyright (c) 2006-2025 RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2025-2-3 yekai first version 9 */ 10 11 #include "board.h" 12 13 /** 14 * @brief System Clock Configuration 15 * @retval None 16 */ SystemClock_Config(void)17void SystemClock_Config(void) { 18 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 19 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 20 21 /** Supply configuration update enable 22 */ 23 HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY); 24 25 /** Configure the main internal regulator output voltage 26 */ 27 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 28 29 while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 30 31 /** Initializes the RCC Oscillators according to the specified parameters 32 * in the RCC_OscInitTypeDef structure. 33 */ 34 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 35 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 36 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 37 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 38 RCC_OscInitStruct.PLL.PLLM = 5; 39 RCC_OscInitStruct.PLL.PLLN = 110; 40 RCC_OscInitStruct.PLL.PLLP = 1; 41 RCC_OscInitStruct.PLL.PLLQ = 5; 42 RCC_OscInitStruct.PLL.PLLR = 2; 43 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 44 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 45 RCC_OscInitStruct.PLL.PLLFRACN = 0; 46 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 47 Error_Handler(); 48 } 49 50 /** Initializes the CPU, AHB and APB buses clocks 51 */ 52 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 53 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 54 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; 55 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 56 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 57 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 58 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 59 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 60 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 61 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 62 63 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { 64 Error_Handler(); 65 } 66 } 67 MPU_Config(void)68int MPU_Config(void) { 69 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 70 71 /* Disables the MPU */ 72 HAL_MPU_Disable(); 73 74 MPU_InitStruct.Enable = MPU_REGION_ENABLE; 75 76 // ITCM 0x00000000 64K ReadOnly 77 MPU_InitStruct.Number = MPU_REGION_NUMBER0; 78 MPU_InitStruct.BaseAddress = 0x00000000; 79 MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; 80 MPU_InitStruct.SubRegionDisable = 0x0; 81 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 82 MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RO_URO; 83 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; 84 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 85 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 86 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 87 HAL_MPU_ConfigRegion(&MPU_InitStruct); 88 89 // DTCM 0x20000000 128K ReadWrite 90 MPU_InitStruct.Number = MPU_REGION_NUMBER1; 91 MPU_InitStruct.BaseAddress = 0x20000000; 92 MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 93 MPU_InitStruct.SubRegionDisable = 0x0; 94 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 95 MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RW_URO; 96 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; 97 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 98 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 99 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 100 HAL_MPU_ConfigRegion(&MPU_InitStruct); 101 102 // RAMD1 0x24000000 320K ReadWrite 103 MPU_InitStruct.Number = MPU_REGION_NUMBER2; 104 MPU_InitStruct.BaseAddress = 0x24000000; 105 MPU_InitStruct.Size = MPU_REGION_SIZE_512KB; 106 MPU_InitStruct.SubRegionDisable = 0x0; 107 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 108 MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RW_URO; 109 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; 110 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 111 MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; 112 MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 113 HAL_MPU_ConfigRegion(&MPU_InitStruct); 114 115 // RAMD2 0x30000000 32K ReadWrite DMABuffer 116 MPU_InitStruct.Number = MPU_REGION_NUMBER3; 117 MPU_InitStruct.BaseAddress = 0x30000000; 118 MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; 119 MPU_InitStruct.SubRegionDisable = 0x0; 120 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 121 MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RW_URO; 122 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 123 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 124 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 125 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 126 HAL_MPU_ConfigRegion(&MPU_InitStruct); 127 128 // RAMD3 0x38000000 16K ReadWrite DMABuffer 129 MPU_InitStruct.Number = MPU_REGION_NUMBER4; 130 MPU_InitStruct.BaseAddress = 0x38000000; 131 MPU_InitStruct.Size = MPU_REGION_SIZE_16KB; 132 MPU_InitStruct.SubRegionDisable = 0x0; 133 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 134 MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RW_URO; 135 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 136 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 137 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 138 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 139 HAL_MPU_ConfigRegion(&MPU_InitStruct); 140 141 // FLASH 0x90000000 128M ReadOnly 142 MPU_InitStruct.Number = MPU_REGION_NUMBER5; 143 MPU_InitStruct.BaseAddress = 0x90000000; 144 MPU_InitStruct.Size = MPU_REGION_SIZE_128MB; 145 MPU_InitStruct.SubRegionDisable = 0x0; 146 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 147 MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RO_URO; 148 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; 149 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 150 MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; 151 MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 152 HAL_MPU_ConfigRegion(&MPU_InitStruct); 153 154 /* Enables the MPU */ 155 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 156 157 return 0; 158 } 159 160 INIT_BOARD_EXPORT(MPU_Config); 161 162 #if defined(__GNUC__) && !defined(__ARMCC_VERSION) 163 164 extern void SystemInit(void); 165 166 extern int entry(void); 167 168 #pragma GCC push_options 169 #pragma GCC optimize ("O0") 170 171 extern volatile uint32_t _ramfunc_start_lma; 172 extern volatile uint32_t _ramfunc_start_vma; 173 extern volatile uint32_t _ramfunc_end; 174 175 extern volatile uint32_t _data_start_lma; 176 extern volatile uint32_t _data_start_vma; 177 extern volatile uint32_t _data_end; 178 179 extern volatile uint32_t _sbss; 180 extern volatile uint32_t _ebss; 181 182 __attribute__((used, section(".text.reset_handler"))) Reset_Handler(void)183void Reset_Handler(void) { 184 __asm volatile ("ldr sp, =_estack"); 185 volatile uint32_t *pui32Src; 186 volatile uint32_t *pui32Dest; 187 188 // copy itcm 189 for (pui32Src = &_ramfunc_start_lma, pui32Dest = &_ramfunc_start_vma; 190 pui32Dest < &_ramfunc_end; 191 pui32Src++, pui32Dest++) { 192 *pui32Dest = *pui32Src; 193 } 194 195 // copy data 196 for (pui32Src = &_data_start_lma, pui32Dest = &_data_start_vma; 197 pui32Dest < &_data_end; 198 pui32Src++, pui32Dest++) { 199 *pui32Dest = *pui32Src; 200 } 201 202 // init bss 203 for (pui32Dest = &_sbss; 204 pui32Dest < &_ebss; 205 pui32Dest++) { 206 *pui32Dest = 0; 207 } 208 209 SystemInit(); 210 211 entry(); 212 } 213 214 #pragma GCC pop_options 215 216 #endif