1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 SummerGift first version 9 */ 10 11 #include "board.h" 12 SystemClock_Config(void)13void SystemClock_Config(void) 14 { 15 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 16 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 17 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 18 19 /** Supply configuration update enable 20 */ 21 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 22 /** Configure the main internal regulator output voltage 23 */ 24 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 25 26 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 27 /** Configure LSE Drive Capability 28 */ 29 HAL_PWR_EnableBkUpAccess(); 30 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); 31 /** Macro to configure the PLL clock source 32 */ 33 __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); 34 /** Initializes the CPU, AHB and APB busses clocks 35 */ 36 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE 37 |RCC_OSCILLATORTYPE_LSE; 38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 39 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 40 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 41 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 42 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 43 RCC_OscInitStruct.PLL.PLLM = 5; 44 RCC_OscInitStruct.PLL.PLLN = 160; 45 RCC_OscInitStruct.PLL.PLLP = 2; 46 RCC_OscInitStruct.PLL.PLLQ = 4; 47 RCC_OscInitStruct.PLL.PLLR = 2; 48 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 49 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 50 RCC_OscInitStruct.PLL.PLLFRACN = 0; 51 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 52 { 53 Error_Handler(); 54 } 55 /** Initializes the CPU, AHB and APB busses clocks 56 */ 57 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 58 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 59 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; 60 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 61 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 62 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 63 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 64 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 65 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 66 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 67 68 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 69 { 70 Error_Handler(); 71 } 72 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_LTDC 73 |RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_USART1 74 |RCC_PERIPHCLK_SPI2|RCC_PERIPHCLK_QSPI 75 |RCC_PERIPHCLK_FMC; 76 PeriphClkInitStruct.PLL3.PLL3M = 5; 77 PeriphClkInitStruct.PLL3.PLL3N = 160; 78 PeriphClkInitStruct.PLL3.PLL3P = 2; 79 PeriphClkInitStruct.PLL3.PLL3Q = 2; 80 PeriphClkInitStruct.PLL3.PLL3R = 88; 81 PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2; 82 PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; 83 PeriphClkInitStruct.PLL3.PLL3FRACN = 0; 84 PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK; 85 PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; 86 PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; 87 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 88 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 89 PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 91 { 92 Error_Handler(); 93 } 94 } 95 96