1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021-12-14 supperthomas The first version for STM32H7xx 9 */ 10 11 #ifndef __SDRAM_PORT_H__ 12 #define __SDRAM_PORT_H__ 13 14 /* parameters for sdram peripheral */ 15 /* Bank1 or Bank2 */ 16 #define SDRAM_TARGET_BANK 1 17 /* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */ 18 #define SDRAM_BANK_ADDR ((uint32_t)0XC0000000) 19 /* data width: 8, 16, 32 */ 20 #define SDRAM_DATA_WIDTH 32 21 /* column bit numbers: 8, 9, 10, 11 */ 22 #define SDRAM_COLUMN_BITS 9 23 /* row bit numbers: 11, 12, 13 */ 24 #define SDRAM_ROW_BITS 12 25 /* cas latency clock number: 1, 2, 3 */ 26 #define SDRAM_CAS_LATENCY 2 27 /* read pipe delay: 0, 1, 2 */ 28 #define SDRAM_RPIPE_DELAY 0 29 /* clock divid: 2, 3 */ 30 #define SDCLOCK_PERIOD 2 31 /* refresh rate counter */ 32 #define SDRAM_REFRESH_RATE (64) // ms 33 #define SDRAM_FREQUENCY (100000) // 100 MHz 34 #define SDRAM_REFRESH_CYCLES 4096 35 #define SDRAM_REFRESH_COUNT (SDRAM_REFRESH_RATE * SDRAM_FREQUENCY / SDRAM_REFRESH_CYCLES - 20) //((uint32_t)0x02A5) 36 #define SDRAM_SIZE (32 * 1024 * 1024) 37 38 /* Timing configuration for W9825G6KH-6 */ 39 /* 100 MHz of HCKL3 clock frequency (200MHz/2) */ 40 /* TMRD: 2 Clock cycles */ 41 #define LOADTOACTIVEDELAY 2 42 /* TXSR: 8x10ns */ 43 #define EXITSELFREFRESHDELAY 7 44 /* TRAS: 5x10ns */ 45 #define SELFREFRESHTIME 5 46 /* TRC: 7x10ns */ 47 #define ROWCYCLEDELAY 6 48 /* TWR: 2 Clock cycles */ 49 #define WRITERECOVERYTIME 3 50 /* TRP: 2x10ns */ 51 #define RPDELAY 2 52 /* TRCD: 2x10ns */ 53 #define RCDDELAY 2 54 55 /* memory mode register */ 56 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) 57 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) 58 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) 59 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) 60 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) 61 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) 62 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) 63 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) 64 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 65 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 66 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) 67 68 #endif 69