1# STM32H743-Nucleo BSP Introduction 2 3[中文](README_zh.md) 4 5## MCU: STM32H743ZI @480MHz, 2MB FLASH, 1MB RAM 6 7STM32H742xI/G and STM32H743xI/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H742xI/G and STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. 8 9STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. 10 11#### KEY FEATURES 12 13- Core 14 - 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions 15- Memories 16 - Up to 2 Mbytes of Flash memory with read-while-write support 17 - Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain 18 - Dual mode Quad-SPI memory interface running up to 133 MHz 19 - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 100 MHz in Synchronous mode 20 - CRC calculation unit 21- Security 22 - ROP, PC-ROP, active tamper 23- General-purpose input/outputs 24 - Up to 168 I/O ports with interrupt capability 25- Reset and power management 26 - 3 separate power domains which can be independently clock-gated or switched off: 27 - D1: high-performance capabilities 28 - D2: communication peripherals and timers 29 - D3: reset/clock control/power management 30 - 1.62 to 3.6 V application supply and I/Os 31 - POR, PDR, PVD and BOR 32 - Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs 33 - Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry 34 - Voltage scaling in Run and Stop mode (6 configurable ranges) 35 - Backup regulator (~0.9 V) 36 - Voltage reference for analog peripheral/VREF+ 37 - Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging 38- Low-power consumption 39 - VBAT battery operating mode with charging capability 40 - CPU and domain power state monitoring pins 41 - 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON) 42- Clock management 43 - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI 44 - External oscillators: 4-48 MHz HSE, 32.768 kHz LSE 45 - 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode 46- Interconnect matrix 47 48- 4 DMA controllers to unload the CPU 49 - 1× high-speed master direct memory access controller (MDMA) with linked list support 50 - 2× dual-port DMAs with FIFO 51 - 1× basic DMA with request router capabilities 52- Up to 35 communication peripherals 53 - 4× I2Cs FM+ interfaces (SMBus/PMBus) 54 - 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART 55 - 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) 56 - 4x SAIs (serial audio interface) 57 - SPDIFRX interface 58 - SWPMI single-wire protocol master I/F 59 - MDIO Slave interface 60 - 2× SD/SDIO/MMC interfaces (up to 125 MHz) 61 - 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) 62 - 2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD 63 - Ethernet MAC interface with DMA controller 64 - HDMI-CEC 65 - 8- to 14-bit camera interface (up to 80 MHz) 66- 11 analog peripherals 67 - 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) 68 - 1× temperature sensor 69 - 2× 12-bit D/A converters (1 MHz) 70 - 2× ultra-low-power comparators 71 - 2× operational amplifiers (7.3 MHz bandwidth) 72 - 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters 73- Graphics 74 - LCD-TFT controller up to XGA resolution 75 - Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load 76 - Hardware JPEG Codec 77- Up to 22 timers and watchdogs 78 - 1× high-resolution timer (2.1 ns max resolution) 79 - 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz) 80 - 2× 16-bit advanced motor control timers (up to 240 MHz) 81 - 10× 16-bit general-purpose timers (up to 240 MHz) 82 - 5× 16-bit low-power timers (up to 240 MHz) 83 - 2× watchdogs (independent and window) 84 - 1× SysTick timer 85 - RTC with sub-second accuracy and hardware calendar 86- Debug mode 87 - SWD & JTAG interfaces 88 - 4-Kbyte Embedded Trace Buffer 89- True random number generators (3 oscillators each) 90- 96-bit unique ID 91 92 93 94## Read more 95 96| Documents | Description | 97| :----------------------------------------------------------: | :----------------------------------------------------------: | 98| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | 99| [STM32H743ZI ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32h743zi.html#documentation) | STM32H743ZI datasheet and other resources | 100 101 102 103## Maintained By 104 105[tyustli](https://github.com/tyustli) 106 107 108 109## Translated By 110 111Meco Man @ RT-Thread Community 112 113> jiantingman@foxmail.com 114> 115> https://github.com/mysterywolf