1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-10-26 zylx first version 9 */ 10 11 #include "board.h" 12 13 /** 14 * @brief System Clock Configuration 15 * @retval None 16 */ SystemClock_Config(void)17void SystemClock_Config(void) 18 { 19 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 20 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 21 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 22 23 /** Supply configuration update enable 24 */ 25 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 26 /** Configure the main internal regulator output voltage 27 */ 28 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 29 30 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 31 /** Macro to configure the PLL clock source 32 */ 33 __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); 34 /** Initializes the CPU, AHB and APB busses clocks 35 */ 36 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; 37 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 39 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 40 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 41 RCC_OscInitStruct.PLL.PLLM = 5; 42 RCC_OscInitStruct.PLL.PLLN = 160; 43 RCC_OscInitStruct.PLL.PLLP = 2; 44 RCC_OscInitStruct.PLL.PLLQ = 2; 45 RCC_OscInitStruct.PLL.PLLR = 2; 46 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 47 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 48 RCC_OscInitStruct.PLL.PLLFRACN = 0; 49 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 50 { 51 Error_Handler(); 52 } 53 /** Initializes the CPU, AHB and APB busses clocks 54 */ 55 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 56 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 57 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; 58 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 59 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 60 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 61 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 62 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 63 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 64 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 65 66 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 67 { 68 Error_Handler(); 69 } 70 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_USART1 71 |RCC_PERIPHCLK_RNG|RCC_PERIPHCLK_SDMMC 72 |RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_QSPI; 73 PeriphClkInitStruct.PLL2.PLL2M = 5; 74 PeriphClkInitStruct.PLL2.PLL2N = 192; 75 PeriphClkInitStruct.PLL2.PLL2P = 2; 76 PeriphClkInitStruct.PLL2.PLL2Q = 2; 77 PeriphClkInitStruct.PLL2.PLL2R = 2; 78 PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 79 PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 80 PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 81 PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; 82 PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; 83 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 84 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 85 PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 86 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 87 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 88 { 89 Error_Handler(); 90 } 91 } 92 93 /** 94 * Function ota_app_vtor_reconfig 95 * Description Set Vector Table base location to the start addr of app(RT_APP_PART_ADDR). 96 */ ota_app_vtor_reconfig(void)97static int ota_app_vtor_reconfig(void) 98 { 99 #define RT_APP_PART_ADDR 0x08020000 100 #define NVIC_VTOR_MASK 0x3FFFFF80 101 /* Set the Vector Table base location by user application firmware definition */ 102 SCB->VTOR = RT_APP_PART_ADDR & NVIC_VTOR_MASK; 103 104 return 0; 105 } 106 INIT_BOARD_EXPORT(ota_app_vtor_reconfig); 107