1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-10-26 zylx first version 9 */ 10 11 #include "board.h" 12 13 /** 14 * @brief System Clock Configuration 15 * @retval None 16 */ SystemClock_Config(void)17void SystemClock_Config(void) 18 { 19 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 20 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 21 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 22 23 /** Supply configuration update enable 24 */ 25 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 26 /** Configure the main internal regulator output voltage 27 */ 28 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 29 30 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 31 32 /** Initializes the RCC Oscillators according to the specified parameters 33 * in the RCC_OscInitTypeDef structure. 34 */ 35 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; 36 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 37 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 39 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 40 RCC_OscInitStruct.PLL.PLLM = 5; 41 RCC_OscInitStruct.PLL.PLLN = 192; 42 RCC_OscInitStruct.PLL.PLLP = 2; 43 RCC_OscInitStruct.PLL.PLLQ = 2; 44 RCC_OscInitStruct.PLL.PLLR = 2; 45 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 46 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 47 RCC_OscInitStruct.PLL.PLLFRACN = 0; 48 49 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 50 { 51 Error_Handler(); 52 } 53 54 /** Initializes the CPU, AHB and APB buses clocks 55 */ 56 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 57 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 58 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; 59 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 60 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 61 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 62 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 63 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 64 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 65 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 66 67 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 68 { 69 Error_Handler(); 70 } 71 72 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_USART3 73 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_SPI4 74 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SDMMC 75 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB 76 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_FMC; 77 PeriphClkInitStruct.PLL2.PLL2M = 2; 78 PeriphClkInitStruct.PLL2.PLL2N = 64; 79 PeriphClkInitStruct.PLL2.PLL2P = 2; 80 PeriphClkInitStruct.PLL2.PLL2Q = 2; 81 PeriphClkInitStruct.PLL2.PLL2R = 4; 82 PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; 83 PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 84 PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 85 PeriphClkInitStruct.PLL3.PLL3M = 5; 86 PeriphClkInitStruct.PLL3.PLL3N = 160; 87 PeriphClkInitStruct.PLL3.PLL3P = 8; 88 PeriphClkInitStruct.PLL3.PLL3Q = 8; 89 PeriphClkInitStruct.PLL3.PLL3R = 24; 90 PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2; 91 PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; 92 PeriphClkInitStruct.PLL3.PLL3FRACN = 0; 93 PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2; 94 PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2; 95 PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; 96 PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL3; 97 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 98 PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; 99 PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; 100 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 101 102 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 103 { 104 Error_Handler(); 105 } 106 107 /** Enable USB Voltage detector 108 */ 109 HAL_PWREx_EnableUSBVoltageDetector(); 110 } 111 112