1 /* 2 * Copyright (c) 2006-2025 RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-12-25 zylx first version 9 * 2020-07-18 wanghaijing add SPECIAL_MODES_REG 10 */ 11 12 #ifndef __DRV_ETH_H__ 13 #define __DRV_ETH_H__ 14 15 #include <rtthread.h> 16 #include <rthw.h> 17 #include <rtdevice.h> 18 #include <board.h> 19 20 /* The PHY basic control register */ 21 #define PHY_BASIC_CONTROL_REG 0x00U 22 #define PHY_RESET_MASK (1<<15) 23 #define PHY_AUTO_NEGOTIATION_MASK (1<<12) 24 25 /* The PHY basic status register */ 26 #define PHY_BASIC_STATUS_REG 0x01U 27 #define PHY_LINKED_STATUS_MASK (1<<2) 28 #define PHY_AUTONEGO_COMPLETE_MASK (1<<5) 29 30 /* The PHY ID one register */ 31 #define PHY_ID1_REG 0x02U 32 33 /* The PHY ID two register */ 34 #define PHY_ID2_REG 0x03U 35 36 /* The PHY SPECIAL MODES REGISTER */ 37 #define PHY_SPECIAL_MODES_REG 0x12U 38 39 /* The PHY auto-negotiate advertise register */ 40 #define PHY_AUTONEG_ADVERTISE_REG 0x04U 41 42 #define PHY_Status_REG 0x1FU 43 #define PHY_FULL_DUPLEX_MASK (1<<4) 44 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 45 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 46 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 47 48 #ifdef PHY_USING_LAN8720A 49 /* The PHY interrupt source flag register. */ 50 #define PHY_INTERRUPT_FLAG_REG 0x1DU 51 /* The PHY interrupt mask register. */ 52 #define PHY_INTERRUPT_MASK_REG 0x1EU 53 #define PHY_LINK_DOWN_MASK (1<<4) 54 #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) 55 56 /* The PHY status register. */ 57 #define PHY_Status_REG 0x1FU 58 #define PHY_10M_MASK (1<<2) 59 #define PHY_100M_MASK (1<<3) 60 #define PHY_FULL_DUPLEX_MASK (1<<4) 61 #endif /* PHY_USING_LAN8720A */ 62 63 #ifdef PHY_USING_DM9161CEP 64 #define PHY_Status_REG 0x11U 65 #define PHY_10M_MASK ((1<<12) || (1<<13)) 66 #define PHY_100M_MASK ((1<<14) || (1<<15)) 67 #define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13)) 68 /* The PHY interrupt source flag register. */ 69 #define PHY_INTERRUPT_FLAG_REG 0x15U 70 /* The PHY interrupt mask register. */ 71 #define PHY_INTERRUPT_MASK_REG 0x15U 72 #define PHY_LINK_CHANGE_FLAG (1<<2) 73 #define PHY_LINK_CHANGE_MASK (1<<9) 74 #define PHY_INT_MASK 0 75 76 #endif /* PHY_USING_DM9161CEP */ 77 78 #ifdef PHY_USING_DP83848C 79 #define PHY_Status_REG 0x10U 80 #define PHY_10M_MASK (1<<1) 81 #define PHY_FULL_DUPLEX_MASK (1<<2) 82 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 83 #define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr)) 84 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 85 #define PHY_INTERRUPT_FLAG_REG 0x12U 86 #define PHY_LINK_CHANGE_FLAG (1<<13) 87 #define PHY_INTERRUPT_CTRL_REG 0x11U 88 #define PHY_INTERRUPT_EN ((1<<0)|(1<<1)) 89 #define PHY_INTERRUPT_MASK_REG 0x12U 90 #define PHY_INT_MASK (1<<5) 91 #endif /* PHY_USING_DP83848C */ 92 #endif /* __DRV_ETH_H__ */ 93