1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023-03-24 spaceman the first version
9 */
10
11 #include <rtthread.h>
12 #include "board.h"
13 #include <drv_common.h>
14
15 #define AXI_SRAM_ADDR (0X24000000)
16 #define AXI_SRAM_SIZE (512*1024)
17 #define SRAM1_ADDR (0X30000000)
18 #define SRAM1_SIZE (128*1024)
19 #define SRAM2_ADDR (0X30020000)
20 #define SRAM2_SIZE (128*1024)
21 #define SRAM3_ADDR (0X30040000)
22 #define SRAM3_SIZE (32*1024)
23 #define SRAM4_ADDR (0X38000000)
24 #define SRAM4_SIZE (64*1024)
25 #define BACKUP_ADDR (0X38800000)
26 #define BACKUP_SIZE (4*1024)
27
28 static struct rt_memheap _heap_axi_sram;
29 static struct rt_memheap _heap_sram1;
30 static struct rt_memheap _heap_sram2;
31 static struct rt_memheap _heap_sram3;
32 static struct rt_memheap _heap_sram4;
33 static struct rt_memheap _heap_backup_sram;
34
35 /**
36 * @brief System Clock Configuration
37 * @retval None
38 */
SystemClock_Config(void)39 void SystemClock_Config(void)
40 {
41 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
42 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
43 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
44
45 /** Supply configuration update enable
46 */
47 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
48 /** Configure the main internal regulator output voltage
49 */
50 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
51
52 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
53 /** Configure LSE Drive Capability
54 */
55 HAL_PWR_EnableBkUpAccess();
56 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
57 /** Initializes the RCC Oscillators according to the specified parameters
58 * in the RCC_OscInitTypeDef structure.
59 */
60 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
61 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
62 RCC_OscInitStruct.LSEState = RCC_LSE_ON;
63 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
64 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
65 RCC_OscInitStruct.PLL.PLLM = 5;
66 RCC_OscInitStruct.PLL.PLLN = 192;
67 RCC_OscInitStruct.PLL.PLLP = 2;
68 RCC_OscInitStruct.PLL.PLLQ = 2;
69 RCC_OscInitStruct.PLL.PLLR = 2;
70 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
71 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
72 RCC_OscInitStruct.PLL.PLLFRACN = 0;
73 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
74 {
75 Error_Handler();
76 }
77 /** Initializes the CPU, AHB and APB buses clocks
78 */
79 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
81 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
82 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
83 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
84 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
85 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
86 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
87 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
88 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
89
90 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
91 {
92 Error_Handler();
93 }
94 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_UART4
95 |RCC_PERIPHCLK_USART1;
96 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
97 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
98 PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
99 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
100 {
101 Error_Handler();
102 }
103 }
104
init_sram(void)105 static int init_sram(void)
106 {
107 __HAL_RCC_D2SRAM1_CLK_ENABLE();
108 __HAL_RCC_D2SRAM2_CLK_ENABLE();
109 __HAL_RCC_D2SRAM3_CLK_ENABLE();
110 rt_memheap_init(&_heap_axi_sram, "axi_sram", (void *)AXI_SRAM_ADDR, AXI_SRAM_SIZE);
111 rt_memheap_init(&_heap_sram1, "sram1", (void *)SRAM1_ADDR, SRAM1_SIZE);
112 rt_memheap_init(&_heap_sram2, "sram2", (void *)SRAM2_ADDR, SRAM2_SIZE);
113 rt_memheap_init(&_heap_sram3, "sram3", (void *)SRAM3_ADDR, SRAM3_SIZE);
114 rt_memheap_init(&_heap_sram4, "sram4", (void *)SRAM4_ADDR, SRAM4_SIZE);
115 rt_memheap_init(&_heap_backup_sram, "bak_sram", (void *)BACKUP_ADDR, BACKUP_SIZE);
116
117 return 0;
118 }
119 INIT_BOARD_EXPORT(init_sram);
120
121 /**
122 * Function ota_app_vtor_reconfig
123 * Description Set Vector Table base location to the start addr of app(RT_APP_PART_ADDR).
124 */
ota_app_vtor_reconfig(void)125 static int ota_app_vtor_reconfig(void)
126 {
127 #define RT_APP_PART_ADDR 0x08020000
128 #define NVIC_VTOR_MASK 0x3FFFFF80
129 /* Set the Vector Table base location by user application firmware definition */
130 SCB->VTOR = RT_APP_PART_ADDR & NVIC_VTOR_MASK;
131
132 return 0;
133 }
134 // INIT_BOARD_EXPORT(ota_app_vtor_reconfig);
135