1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date              Author         Notes
8  * 2024-3-19     RuiXuan Zhang   first version
9  */
10 
11 #include "board.h"
12 
13 /**
14   * @brief System Clock Configuration
15   * @retval None
16   */
SystemClock_Config(void)17 void SystemClock_Config(void) {
18     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
19     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
20 
21     /** Configure the main internal regulator output voltage
22     */
23     if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
24         Error_Handler();
25     }
26 
27     /** Configure LSE Drive Capability
28     */
29     HAL_PWR_EnableBkUpAccess();
30     __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
31 
32     /** Initializes the RCC Oscillators according to the specified parameters
33     * in the RCC_OscInitTypeDef structure.
34     */
35     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
36     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
37     RCC_OscInitStruct.LSEState = RCC_LSE_ON;
38     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
39     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
40     RCC_OscInitStruct.PLL.PLLM = 1;
41     RCC_OscInitStruct.PLL.PLLN = 20;
42     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
43     RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
44     RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
45     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
46         Error_Handler();
47     }
48 
49     /** Initializes the CPU, AHB and APB buses clocks
50     */
51     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
52                                   | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
53     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
54     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
55     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
56     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
57 
58     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
59         Error_Handler();
60     }
61 }
62 
63 /**
64   * @brief Peripherals Common Clock Configuration
65   * @retval None
66   */
PeriphCommonClock_Config(void)67 void PeriphCommonClock_Config(void) {
68     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
69 
70     /** Initializes the peripherals clock
71     */
72     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADC;
73     PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
74     PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLSAI1;
75     PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
76     PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
77     PeriphClkInit.PLLSAI1.PLLSAI1N = 8;
78     PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
79     PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
80     PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
81     PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK | RCC_PLLSAI1_ADC1CLK;
82     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
83         Error_Handler();
84     }
85 }
86