1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2009-01-05 Bernard first implementation 9 * 2019-05-09 Zero-Free Adding multiple configurations for system clock frequency 10 */ 11 12 #include <board.h> 13 #include <drv_common.h> 14 SystemClock_Config(void)15void SystemClock_Config(void) 16 { 17 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 18 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 19 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 20 21 /** Configure LSE Drive Capability 22 */ 23 HAL_PWR_EnableBkUpAccess(); 24 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); 25 /** Initializes the CPU, AHB and APB busses clocks 26 */ 27 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; 28 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 29 RCC_OscInitStruct.MSIState = RCC_MSI_ON; 30 RCC_OscInitStruct.MSICalibrationValue = 0; 31 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; 32 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 33 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; 34 RCC_OscInitStruct.PLL.PLLM = 1; 35 RCC_OscInitStruct.PLL.PLLN = 40; 36 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 37 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 38 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 39 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 40 { 41 Error_Handler(); 42 } 43 /** Initializes the CPU, AHB and APB busses clocks 44 */ 45 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 46 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 47 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 48 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 49 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 50 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 51 52 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 53 { 54 Error_Handler(); 55 } 56 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_USB; 57 PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; 58 PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; 59 PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; 60 PeriphClkInit.PLLSAI1.PLLSAI1M = 1; 61 PeriphClkInit.PLLSAI1.PLLSAI1N = 24; 62 PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2; 63 PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; 64 PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; 65 PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; 66 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 67 { 68 Error_Handler(); 69 } 70 /** Configure the main internal regulator output voltage 71 */ 72 if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) 73 { 74 Error_Handler(); 75 } 76 /** Enable MSI Auto calibration 77 */ 78 HAL_RCCEx_EnableMSIPLLMode(); 79 } 80 81