1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-12-04 zylx first version
9 */
10
11 #include <rtthread.h>
12 #include <rtdevice.h>
13 #include <board.h>
14
15 #ifdef BSP_USING_SRAM
16 #include <sram_port.h>
17
18 #define DRV_DEBUG
19 #define LOG_TAG "drv.sram"
20 #include <drv_log.h>
21
22 static SRAM_HandleTypeDef hsram;
23 static FMC_NORSRAM_TimingTypeDef SRAM_Timing;
24 #ifdef RT_USING_MEMHEAP_AS_HEAP
25 static struct rt_memheap system_heap;
26 #endif
27
SRAM_Init(void)28 static int SRAM_Init(void)
29 {
30 int result = RT_EOK;
31
32 /* SRAM device configuration */
33 hsram.Instance = FMC_NORSRAM_DEVICE;
34 hsram.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
35
36 /* SRAM device configuration */
37 SRAM_Timing.AddressSetupTime = ADDRESSSETUPTIME;
38 SRAM_Timing.AddressHoldTime = ADDRESSHOLDTIME; /* Min value, Don't care on SRAM Access mode A */
39 SRAM_Timing.DataSetupTime = DATASETUPTIME;
40 SRAM_Timing.DataHoldTime = DATAHOLDTIME;
41 SRAM_Timing.BusTurnAroundDuration = BUSTURNAROUNDDURATION;
42 SRAM_Timing.CLKDivision = CLKDIVISION; /* Min value, Don't care on SRAM Access mode A */
43 SRAM_Timing.DataLatency = DATALATENCY; /* Min value, Don't care on SRAM Access mode A */
44 SRAM_Timing.AccessMode = ACCESSMODE;
45
46 hsram.Init.NSBank = FMC_NORSRAM_BANK1;
47 hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
48 hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
49 #if SRAM_DATA_WIDTH == 8
50 hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_8;
51 #elif SRAM_DATA_WIDTH == 16
52 hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
53 #else
54 hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
55 #endif
56 hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
57 hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
58 hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
59 hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
60 hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
61 hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
62 hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
63 hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
64 hsram.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
65 hsram.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
66 hsram.Init.NBLSetupTime = 0;
67 hsram.Init.PageSize = FMC_PAGE_SIZE_NONE;
68
69 /* Initialize the SRAM controller */
70 if (HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing) != HAL_OK)
71 {
72 LOG_E("SRAM init failed!");
73 result = -RT_ERROR;
74 }
75 else
76 {
77 LOG_D("sram init success, mapped at 0x%X, size is %d bytes, data width is %d", SRAM_BANK_ADDR, SRAM_SIZE, SRAM_DATA_WIDTH);
78 #ifdef RT_USING_MEMHEAP_AS_HEAP
79 /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
80 rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
81 #endif
82 }
83
84 return result;
85 }
86 INIT_BOARD_EXPORT(SRAM_Init);
87
88 #ifdef DRV_DEBUG
89 #ifdef FINSH_USING_MSH
sram_test(void)90 int sram_test(void)
91 {
92 int i = 0;
93 uint32_t start_time = 0, time_cast = 0;
94 #if SRAM_DATA_WIDTH == 8
95 char data_width = 1;
96 uint8_t data = 0;
97 uint8_t *ptr = (uint8_t *)SRAM_BANK_ADDR;
98 #elif SRAM_DATA_WIDTH == 16
99 char data_width = 2;
100 uint16_t data = 0;
101 uint16_t *ptr = (uint16_t *)SRAM_BANK_ADDR;
102 #else
103 char data_width = 4;
104 uint32_t data = 0;
105 uint32_t *ptr = (uint32_t *)SRAM_BANK_ADDR;
106 #endif
107
108 /* write data */
109 LOG_D("Writing the %ld bytes data, waiting....", SRAM_SIZE);
110 start_time = rt_tick_get();
111 for (i = 0; i < SRAM_SIZE / data_width; i++)
112 {
113 #if SRAM_DATA_WIDTH == 8
114 ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
115 #elif SRAM_DATA_WIDTH == 16
116 ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
117 #else
118 ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
119 #endif
120 }
121 time_cast = rt_tick_get() - start_time;
122 LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
123 time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
124
125 /* read data */
126 LOG_D("start Reading and verifying data, waiting....");
127 for (i = 0; i < SRAM_SIZE / data_width; i++)
128 {
129 #if SRAM_DATA_WIDTH == 8
130 data = ((__IO uint8_t *)ptr)[i];
131 if (data != 0x55)
132 {
133 LOG_E("SRAM test failed!");
134 break;
135 }
136 #elif SRAM_DATA_WIDTH == 16
137 data = ((__IO uint16_t *)ptr)[i];
138 if (data != 0x5555)
139 {
140 LOG_E("SRAM test failed!");
141 break;
142 }
143 #else
144 data = ((__IO uint32_t *)ptr)[i];
145 if (data != 0x55555555)
146 {
147 LOG_E("SRAM test failed!");
148 break;
149 }
150 #endif
151 }
152
153 if (i >= SRAM_SIZE / data_width)
154 {
155 LOG_D("SRAM test success!");
156 }
157
158 return RT_EOK;
159 }
160 MSH_CMD_EXPORT(sram_test, sram test);
161 #endif /* FINSH_USING_MSH */
162 #endif /* DRV_DEBUG */
163 #endif /* BSP_USING_SRAM */
164