1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-12-04     zylx         The first version for STM32F4xx
9  */
10 
11 #ifndef __SDRAM_PORT_H__
12 #define __SDRAM_PORT_H__
13 
14 /* parameters for sdram peripheral */
15 /* Bank1 */
16 #define SRAM_TARGET_BANK                1
17 /* stm32f4 Bank1:0x60000000 */
18 #define SRAM_BANK_ADDR                  ((uint32_t)0x60000000)
19 /* data width: 8, 16, 32 */
20 #define SRAM_DATA_WIDTH                 16
21 /* sram size */
22 #define SRAM_SIZE                       ((uint32_t)0x200000)
23 
24 /* Timing configuration for IS61WV102416BLL-10MLI */
25 #define ADDRESSSETUPTIME                2
26 #define ADDRESSHOLDTIME                 1
27 #define DATASETUPTIME                   1
28 #define DATAHOLDTIME                    1
29 #define BUSTURNAROUNDDURATION           0
30 #define CLKDIVISION                     2
31 #define DATALATENCY                     2
32 #define ACCESSMODE                      FMC_ACCESS_MODE_A
33 /* Timing configuration for IS61WV102416BLL-10MLI */
34 
35 #endif
36