1# NUCLEO-STM32L552ZE-Q- BSP Introduction
2
3[中文](README_zh.md)
4
5## MCU: STM32L552ZE @110MHz, 256 KB FLASH,  156KB RAM
6
7The STM32L552xx devices are an ultra-low-power microcontrollers family (STM32L5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 110 MHz. The Cortex-M33 core features a single-precision floating-point unit (FPU), which supports all the Arm® single-precision data-processing instructions and all the data types. The Cortex-M33 core also implements a full set of DSP (digital signal processing) instructions, TrustZone aware support and a memory protection unit (MPU) which enhances the applications security. These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), an OctoSPI Flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
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9The STM32L552xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, secure and hide protection areas. These devices offer two fast 12-bit ADC (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). In addition, up to 22 capacitive sensing channels are available.
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11#### KEY FEATURES
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13- Core
14  - Ultra-low-power with FPU Arm Cortex-M33 with Trust Zone
15- Memories
16  - Up to 512 Kbytes Flash, two banks read-while-write
17  - 256 Kbytes of SRAM including 64 Kbytes with hardware parity check
18  - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories
19  - OCTOSPI memory interface
20- Security
21  - Arm TrustZone with the ARMv8-M mainline security extension
22  - Up to 8 configurable SAU regions
23  - RDP, active tamper, secure firmware upgrade support, secure hide protection
24  - TrustZone aware and securable peripherals
25- General-purpose input/outputs
26  - Up to 114 fast I/Os with interrupt capability most 5 V-tolerant and up to 14 I/Os with independent supply down to 1.08 V
27- Reset and power management
28  - 3 separate power domains which can be independently clock-gated or switched off:
29    - D1: high-performance capabilities
30    - D2: communication peripherals and timers
31    - D3: reset/clock control/power management
32  - 1.62 to 3.6 V application supply and I/Os
33  - POR, PDR, PVD and BOR
34  - Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
35  - Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
36  - Voltage scaling in Run and Stop mode (6 configurable ranges)
37  - Backup regulator (~0.9 V)
38  - Voltage reference for analog peripheral/VREF+
39  - Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging
40- Low-power consumption
41  - VBAT battery operating mode with charging capability
42  - CPU and domain power state monitoring pins
43  - 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)
44- Clock management
45  - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
46  - External oscillators: 4-48 MHz HSE, 32.768 kHz LSE
47  - 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode
48- Interconnect matrix
49- 4 DMA controllers to unload the CPU
50  - 1× high-speed master direct memory access controller (MDMA) with linked list support
51  - 2× dual-port DMAs with FIFO
52  - 1× basic DMA with request router capabilities
53- Up to 35 communication peripherals
54  - 4× I2Cs FM+ interfaces (SMBus/PMBus)
55  - 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
56  - 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz)
57  - 4x SAIs (serial audio interface)
58  - SPDIFRX interface
59  - SWPMI single-wire protocol master I/F
60  - MDIO Slave interface
61  - 2× SD/SDIO/MMC interfaces (up to 125 MHz)
62  - 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
63  - 2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD
64  - Ethernet MAC interface with DMA controller
65  - HDMI-CEC
66  - 8- to 14-bit camera interface (up to 80 MHz)
67- 11 analog peripherals
68  - 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS)
69  - 1× temperature sensor
70  - 2× 12-bit D/A converters (1 MHz)
71  - 2× ultra-low-power comparators
72  - 2× operational amplifiers (7.3 MHz bandwidth)
73  - 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
74- Graphics
75  - LCD-TFT controller up to XGA resolution
76  - Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load
77  - Hardware JPEG Codec
78- Up to 22 timers and watchdogs
79  - 1× high-resolution timer (2.1 ns max resolution)
80  - 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz)
81  - 2× 16-bit advanced motor control timers (up to 240 MHz)
82  - 10× 16-bit general-purpose timers (up to 240 MHz)
83  - 5× 16-bit low-power timers (up to 240 MHz)
84  - 2× watchdogs (independent and window)
85  - 1× SysTick timer
86  - RTC with sub-second accuracy and hardware calendar
87- Debug mode
88  - SWD & JTAG interfaces
89  - 4-Kbyte Embedded Trace Buffer
90- True random number generators (3 oscillators each)
91- 96-bit unique ID
92
93## Read more
94
95|                          Documents                           |                         Description                          |
96| :----------------------------------------------------------: | :----------------------------------------------------------: |
97| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) |
98| [STM32L552ZE ST Official Website]([STM32L552ZE - Ultra-low-power with FPU Arm Cortex-M33 with Trust Zone, MCU 110 MHz with 512 kbytes of Flash memory - STMicroelectronics](https://www.st.com/en/microcontrollers-microprocessors/stm32l552ze.html)) |           STM32L552ZEdatasheet and other resources
99
100## Maintained By
101
102[liukang](https://github.com/liukangcc)
103