1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-11-06 SummerGift first version 9 * 2019-04-09 WillianChan add stm32f469-st-disco bsp 10 * 2020-06-20 thread-liu add stm32mp157-dk1 bsp 11 */ 12 13 #include "board.h" 14 15 void PeriphCommonClock_Config(void); 16 /** 17 * @brief System Clock Configuration 18 * @retval None 19 */ SystemClock_Config(void)20void SystemClock_Config(void) 21 { 22 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 23 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 24 25 /**Configure LSE Drive Capability 26 */ 27 HAL_PWR_EnableBkUpAccess(); 28 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); 29 30 /**Initializes the CPU, AHB and APB busses clocks 31 */ 32 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE 33 |RCC_OSCILLATORTYPE_LSE; 34 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIG; 35 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 36 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 37 RCC_OscInitStruct.HSICalibrationValue = 16; 38 RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1; 39 40 /**PLL1 Config 41 */ 42 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 43 RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE; 44 RCC_OscInitStruct.PLL.PLLM = 3; 45 RCC_OscInitStruct.PLL.PLLN = 81; 46 RCC_OscInitStruct.PLL.PLLP = 1; 47 RCC_OscInitStruct.PLL.PLLQ = 1; 48 RCC_OscInitStruct.PLL.PLLR = 1; 49 RCC_OscInitStruct.PLL.PLLFRACV = 0x800; 50 RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL; 51 RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 52 RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 53 54 /**PLL2 Config 55 */ 56 RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; 57 RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE; 58 RCC_OscInitStruct.PLL2.PLLM = 3; 59 RCC_OscInitStruct.PLL2.PLLN = 66; 60 RCC_OscInitStruct.PLL2.PLLP = 2; 61 RCC_OscInitStruct.PLL2.PLLQ = 1; 62 RCC_OscInitStruct.PLL2.PLLR = 1; 63 RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400; 64 RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL; 65 RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 66 RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 67 68 /**PLL3 Config 69 */ 70 RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; 71 RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE; 72 RCC_OscInitStruct.PLL3.PLLM = 2; 73 RCC_OscInitStruct.PLL3.PLLN = 34; 74 RCC_OscInitStruct.PLL3.PLLP = 2; 75 RCC_OscInitStruct.PLL3.PLLQ = 17; 76 RCC_OscInitStruct.PLL3.PLLR = 37; 77 RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1; 78 RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04; 79 RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL; 80 RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 81 RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 82 83 /**PLL4 Config 84 */ 85 RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON; 86 RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE; 87 RCC_OscInitStruct.PLL4.PLLM = 4; 88 RCC_OscInitStruct.PLL4.PLLN = 99; 89 RCC_OscInitStruct.PLL4.PLLP = 6; 90 RCC_OscInitStruct.PLL4.PLLQ = 8; 91 RCC_OscInitStruct.PLL4.PLLR = 8; 92 RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0; 93 RCC_OscInitStruct.PLL4.PLLFRACV = 0; 94 RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER; 95 RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; 96 RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; 97 98 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 99 { 100 Error_Handler(); 101 } 102 /**RCC Clock Config 103 */ 104 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK 105 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 106 |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4 107 |RCC_CLOCKTYPE_PCLK5|RCC_CLOCKTYPE_MPU; 108 RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1; 109 RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2; 110 RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2; 111 RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1; 112 RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3; 113 RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1; 114 RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2; 115 RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4; 116 RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2; 117 RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2; 118 RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2; 119 120 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) 121 { 122 Error_Handler(); 123 } 124 125 /**Set the HSE division factor for RTC clock 126 */ 127 __HAL_RCC_RTC_HSEDIV(24); 128 129 /* Configure the peripherals common clocks */ 130 if(IS_ENGINEERING_BOOT_MODE()) 131 { 132 PeriphCommonClock_Config(); 133 } 134 } 135 136 137 /** 138 * @brief Peripherals Common Clock Configuration 139 * @retval None 140 */ PeriphCommonClock_Config(void)141void PeriphCommonClock_Config(void) { 142 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 143 144 /** Initializes the common periph clock 145 */ 146 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER; 147 PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE; 148 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { 149 Error_Handler(); 150 } 151 } 152 153 extern void rt_hw_systick_init(void); 154 extern int rt_hw_usart_init(void); rt_hw_board_init()155void rt_hw_board_init() 156 { 157 /* HAL_Init() function is called at the beginning of the program */ 158 HAL_Init(); 159 160 /* enable interrupt */ 161 __set_PRIMASK(0); 162 /* Configure the system clock */ 163 if (IS_ENGINEERING_BOOT_MODE()) { 164 /* Configure the system clock */ 165 SystemClock_Config(); 166 } 167 /* disable interrupt */ 168 __set_PRIMASK(1); 169 170 rt_hw_systick_init(); 171 172 /* Heap initialization */ 173 #if defined(RT_USING_HEAP) 174 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); 175 #endif 176 177 /* Pin driver initialization is open by default */ 178 #ifdef RT_USING_PIN 179 rt_hw_pin_init(); 180 #endif 181 182 /* USART driver initialization is open by default */ 183 #ifdef RT_USING_SERIAL 184 rt_hw_usart_init(); 185 #endif 186 187 /* Set the shell console output device */ 188 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) 189 rt_console_set_device(RT_CONSOLE_DEVICE_NAME); 190 #endif 191 192 #if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO) 193 extern void rt_hw_console_init(void); 194 rt_hw_console_init(); 195 #endif 196 197 /* Board underlying hardware initialization */ 198 #ifdef RT_USING_COMPONENTS_INIT 199 rt_components_board_init(); 200 #endif 201 } 202